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公开(公告)号：US10079610B2
公开(公告)日：2018-09-18
申请号：US15742435
申请日：2016-07-05
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Andreas Kalt , Jaafar Mejri , Martin Pernull
CPC classification number: H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/468 , H03M1/804
Abstract: Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.
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公开(公告)号：US09853655B1
公开(公告)日：2017-12-26
申请号：US15446495
申请日：2017-03-01
Applicant: Infineon Technologies AG
Inventor： Martin Pernull , Peter Bogner , Sven Derksen , Jaafar Mejri
CPC classification number: H03M1/1071 , G01R27/02 , G01R27/2605 , G01R31/016 , H03M1/00 , H03M1/12 , H03M1/46 , H03M1/804
Abstract: In some examples, a method includes controlling a first set of switches to deliver a first voltage signal through a first set of capacitors to a common node. The method also includes controlling a second set of switches to deliver a second voltage signal through a second set of capacitors to the common node, wherein the first set of capacitors is electrically connected to the second set of capacitors by the common node. The method further includes measuring a time duration to discharge the common node. The second voltage signal includes an opposing polarity to the first voltage signal.
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公开(公告)号：US12068754B2
公开(公告)日：2024-08-20
申请号：US17815057
申请日：2022-07-26
Applicant: Infineon Technologies AG
Inventor： Florian Renneke , Andreas Fugger , Jaafar Mejri
CPC classification number: H03M1/1255 , H03M1/1033 , H03M1/1071 , H03M1/1245 , H03M1/38 , H03M1/466
Abstract: An input stage for an analog/digital converter, an analog/digital converter and a method for testing analog/digital converters with successive approximation are disclosed. At an input stage, an input signal is supplied via a first transistor arrangement of a sampling capacitor arrangement. The sampling capacitor arrangement can be optionally connected to ground or to a reference voltage by way of a second transistor arrangement and a switch apparatus.
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公开(公告)号：US20200162059A1
公开(公告)日：2020-05-21
申请号：US16683586
申请日：2019-11-14
Applicant: Infineon Technologies AG
Inventor： Florian Renneke , Jaafar Mejri
Abstract: A method of operating a relaxation oscillator includes determining a measure of a propagation delay of a detection device of a relaxation oscillator and increasing a charging rate of a capacitor device of the relaxation oscillator for a time duration based on the determined measure of the propagation delay.
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公开(公告)号：US11923120B2
公开(公告)日：2024-03-05
申请号：US17074473
申请日：2020-10-19
Applicant: Infineon Technologies AG
Inventor： Marcus Nuebling , Jaafar Mejri
CPC classification number: H01F27/006 , G01R31/62 , H01F27/324 , H01F38/14
Abstract: A circuit is provided that comprises a transformer having a first coil, which is arranged on a substrate, a second coil, which is arranged above the first coil on the substrate, and a dielectric between the first coil and the second coil. The circuit furthermore comprises a resonant circuit, which is couplable to the first coil and/or the second coil to form a resonant loop, wherein a measure of a characteristic frequency of the resonant loop and/or a measure of a power consumption of the resonant loop is able to be tapped off at an output of the resonant circuit.
A corresponding method is also provided.-
Patent Agency Ranking
公开(公告)号：US11841394B2
公开(公告)日：2023-12-12
申请号：US17068711
申请日：2020-10-12
Applicant: Infineon Technologies AG
Inventor： Marcus Nuebling , Jaafar Mejri
IPC: H01L23/522 , H01L23/58 , H01F27/40 , G01R31/28 , H01F27/28 , G01R31/52 , G01R31/62 , H01F27/32 , H03K17/56
CPC classification number: G01R31/2879 , G01R31/2856 , G01R31/52 , G01R31/62 , H01F27/28 , H01F27/2804 , H01F27/32 , H01F27/402 , H01L23/5223 , H01L23/5228 , H01L23/585 , H03K17/56
Abstract: A circuit is provided, comprising a transformer having a first coil that is arranged on a substrate and a second coil that is arranged on the substrate above the first coil, and a dielectric between the first coil and the second coil. The circuit furthermore comprises a guard ring around the transformer. The circuit furthermore comprises a diagnostic circuit (55) that is configured so as to ground the guard ring in a normal operating mode and to measure a measurement voltage or a measurement current at a measurement impedance between the guard ring and the ground potential in a diagnostic operating mode.
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公开(公告)号：US20230228796A1
公开(公告)日：2023-07-20
申请号：US18155460
申请日：2023-01-17
Applicant: Infineon Technologies AG
Inventor： Chern Sia Phillip Lim , Chin Yeong Koh , Jaafar Mejri
Abstract: In accordance with an embodiment, a controller to operate a temperature sensor comprising a transistor assembly is configured to: cause a generation of a first pair of bias currents comprising a first bias current and a second bias current for the transistor assembly; determine a first diode voltage difference of the transistor assembly corresponding to the first pair of bias currents; cause a generation of a second pair of bias currents comprising a third bias current and a fourth bias current for the transistor assembly; determine a second diode voltage difference for the transistor assembly corresponding to the second pair of bias currents; and compare the first diode voltage difference and the second diode voltage difference to determine at least one of functional information and performance information of the temperature sensor.
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公开(公告)号：US20170099062A1
公开(公告)日：2017-04-06
申请号：US15282677
申请日：2016-09-30
Applicant: Infineon Technologies AG
Inventor： Dario Vagni , Peter Bogner , Jaafar Mejri
CPC classification number: H03M1/1071 , H03M1/109 , H03M1/1245
Abstract: A method for use in testing an analog-to-digital converter. The method includes providing a set of bins, varying a voltage, taking samples of the voltage, providing a selection flag, associating each sample with one bin of the set of bins, and observing a number of samples associated with the bins. An apparatus includes an analog-to-digital converter configured to convert a voltage at an input node to a digital representation provided at an output node. The input node is configured to be coupled to a voltage generator. A sample select unit is configured to determine if a voltage at the input node at least equals a first threshold level and does not exceed a second threshold level. The apparatus is configured, based on the determining, to selectively associate the digital representation with a bin of a set of bins.
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公开(公告)号：US20230045504A1
公开(公告)日：2023-02-09
申请号：US17815057
申请日：2022-07-26
Applicant: Infineon Technologies AG
Inventor： Florian Renneke , Andreas Fugger , Jaafar Mejri
Abstract: An input stage for an analog/digital converter, an analog/digital converter and a method for testing analog/digital converters with successive approximation are disclosed. At an input stage, an input signal is supplied via a first transistor arrangement of a sampling capacitor arrangement. The sampling capacitor arrangement can be optionally connected to ground or to a reference voltage by way of a second transistor arrangement and a switch apparatus.
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公开(公告)号：US20180198460A1
公开(公告)日：2018-07-12
申请号：US15742435
申请日：2016-07-05
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Andreas Kalt , Jaafar Mejri , Martin Pernull
IPC: H03M1/10
CPC classification number: H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/468 , H03M1/804
Abstract: Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.
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