System and method for analog to digital conversion

    公开(公告)号:US09742430B1

    公开(公告)日:2017-08-22

    申请号:US15242265

    申请日:2016-08-19

    CPC classification number: H03M3/462

    Abstract: In some embodiments, a method of operating a sigma-delta analog-to-digital converter (ADC) includes converting an analog input signal into a sequence of digital data using a sigma-delta modulator of the sigma-delta ADC, setting a first configuration for a decimation filter of the sigma-delta ADC according to a first condition of a measurement window, filtering the sequence of digital data using a low-pass filter (LPF) of the decimation filter, and in response to a change in the measurement window, setting a second configuration for the decimation filter according to a second condition of the measurement window.

    Transistor bridge failure test
    4.
    发明授权

    公开(公告)号:US11686781B2

    公开(公告)日:2023-06-27

    申请号:US16932435

    申请日:2020-07-17

    CPC classification number: G01R31/42 G01R19/16528 G01R31/44 G01R31/50 G01R31/52

    Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

    System and method of monitoring a switched-mode power supply

    公开(公告)号:US10917012B1

    公开(公告)日:2021-02-09

    申请号:US16593157

    申请日:2019-10-04

    Abstract: In accordance with an embodiment, a method includes driving a predetermined load using a driver circuit according to a drive pattern; supplying power to the driver circuit using a switched-mode power supply (SMPS) configured to be coupled to at least one external component; and verifying functionality of the SMPS while driving the predetermined load. Verifying the functionality includes monitoring at least one operating parameter of the SMPS, where the at least one operating parameter of the SMPS is dependent on the drive pattern and the at least one external component, comparing the at least one operating parameter to at least one expected operating parameter to form a first comparison result, and indicating an error condition based on the first comparison result.

    TRANSISTOR BRIDGE FAILURE TEST
    6.
    发明申请

    公开(公告)号:US20170276715A1

    公开(公告)日:2017-09-28

    申请号:US15077524

    申请日:2016-03-22

    Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

    System and method of synchronizing a switching signal

    公开(公告)号:US11539313B2

    公开(公告)日:2022-12-27

    申请号:US16003944

    申请日:2018-06-08

    Abstract: In accordance with an embodiment, a method includes generating a clock signal; generating a switching signal based on the clock signal; generating a synchronization signal having an edge transition corresponding to a predetermined phase of the switching signal; transmitting the synchronization signal to a master controller; receiving a frequency adjustment command from the master controller based on the transmitted synchronization signal; and adjusting a frequency of the clock signal based on the frequency adjustment command.

    Transistor bridge failure test
    8.
    发明授权

    公开(公告)号:US10746806B2

    公开(公告)日:2020-08-18

    申请号:US15077524

    申请日:2016-03-22

    Abstract: A driver circuit arrangement for driving a transistor bridge, which includes at least a first half-bridge composed of a low-side transistor and a high-side transistor, is described herein. In accordance with one example of the description, the circuit includes a current source and a detection circuit. The current source is operably coupled to the high-side transistor of the first half-bridge and configured to supply a test current to the first half bridge. The detection circuit is configured to compare a voltage sense signal, which represents the voltage across the high-side transistor of the first half-bridge, with at least one first threshold to detect, dependent on the result of this comparison, whether a short-circuit is present in the first half-bridge.

    System and method of monitoring a switching transistor

    公开(公告)号:US10895601B2

    公开(公告)日:2021-01-19

    申请号:US16409131

    申请日:2019-05-10

    Abstract: In accordance with an embodiment, a method includes using a monitoring circuit disposed on a monolithic integrated circuit to monitor an output signal of a first switching transistor for a first output edge transition at a monitoring terminal of the monolithic integrated circuit; using a time measuring circuit disposed on the monolithic integrated circuit to measure a first time delay between a first input edge transition of a first drive signal and the first output edge transition, where the first drive signal is configured to cause a change of state of the first switching transistor; using an analysis circuit disposed on the monolithic integrated circuit to compare the measured first time delay with a first predetermined threshold to form a first comparison result; and indicating a first error condition based on the first comparison result.

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