公开(公告)号：US20210118986A1

公开(公告)日：2021-04-22

申请号：US17111551

申请日：2020-12-04

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US11888032B2

公开(公告)日：2024-01-30

申请号：US18073860

申请日：2022-12-02

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7813

Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

公开(公告)号：US11462611B2

公开(公告)日：2022-10-04

申请号：US17111551

申请日：2020-12-04

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US20210050421A1

公开(公告)日：2021-02-18

申请号：US16986338

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

公开(公告)号：US12057316B2

公开(公告)日：2024-08-06

申请号：US17476829

申请日：2021-09-16

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Paul Ellinghaus ,  Axel Koenig ,  Caspar Leendertz ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/265 ,  H01L21/04 ,  H01L29/04 ,  H01L29/16 ,  H01L29/167

CPC classification number: H01L21/047 ,  H01L29/045 ,  H01L29/1608

Abstract: A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a direction or a direction.

公开(公告)号：US20240136406A1

公开(公告)日：2024-04-25

申请号：US18398823

申请日：2023-12-28

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7813

Abstract: A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.

公开(公告)号：US20230094032A1

公开(公告)日：2023-03-30

申请号：US18073860

申请日：2022-12-02

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

公开(公告)号：US11552173B2

公开(公告)日：2023-01-10

申请号：US16986338

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

公开(公告)号：US10896952B2

公开(公告)日：2021-01-19

申请号：US16797463

申请日：2020-02-21

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US10586845B1

公开(公告)日：2020-03-10

申请号：US16193296

申请日：2018-11-16

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.