公开(公告)号：US20200152621A1

公开(公告)日：2020-05-14

申请号：US16744693

申请日：2020-01-16

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.

公开(公告)号：US20190157259A1

公开(公告)日：2019-05-23

申请号：US16236741

申请日：2018-12-31

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US10115817B2

公开(公告)日：2018-10-30

申请号：US15157645

申请日：2016-05-18

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Peter Brandl

IPC: H01L29/745 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area, introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, and forming trenches in the second semiconductor layer in the continuous first area.

公开(公告)号：US09349854B2

公开(公告)日：2016-05-24

申请号：US14045925

申请日：2013-10-04

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Peter Brandl

IPC: H01L23/00 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7815

Abstract: A semiconductor device includes a vertical IGFET in a first area of a semiconductor body, the vertical IGFET having a drift zone between a body zone and a drain electrode, the drift zone having a vertical dopant profile of a first conductivity type being a superposition of a first dopant profile declining with increasing distance from the drain electrode and dominating the vertical dopant profile in a first zone next to the drain electrode and a second dopant profile being a broadened peak dopant profile and dominating the vertical dopant profile in a second zone next to the body zone.

Abstract translation: 半导体器件包括在半导体本体的第一区域中的垂直IGFET，垂直IGFET具有在体区和漏极之间的漂移区，漂移区具有第一导电类型的垂直掺杂剂分布， 第一掺杂剂分布随着与漏极电极的距离增加而下降，并且在靠近漏电极的第一区域中支配垂直掺杂剂分布，第二掺杂剂分布是扩展的峰值掺杂物分布，并且在邻近的第二区域中支配垂直掺杂剂分布 身体区域。

公开(公告)号：US10586792B2

公开(公告)日：2020-03-10

申请号：US16236741

申请日：2018-12-31

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40 ,  H01L49/02 ,  H01L29/739 ,  H01L29/808

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20190334000A1

公开(公告)日：2019-10-31

申请号：US16393051

申请日：2019-04-24

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Karl-Heinz Bach ,  Peter Brandl ,  Franz Hirler ,  Andrew Christopher Graeme Wood

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/36 ,  H01L29/78

Abstract: A transistor component includes at least one transistor cell having: a drift region, a source region, a body region and a drain region in a semiconductor body, the body region being arranged between the source and drift regions, and the drift region being arranged between the body and drain regions; a gate electrode arranged adjacent to the body region and dielectrically isolated from the body region by a gate dielectric; and a field electrode arranged adjacent to the drift region and dielectrically isolated from the drift region by a field electrode dielectric. The field electrode dielectric has a thickness that increases in a direction toward the drain region. The drift region has, in a mesa region adjacent to the field electrode, a doping concentration that increases in the direction toward the drain region.

公开(公告)号：US20190051749A1

公开(公告)日：2019-02-14

申请号：US16100496

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Karl-Heinz Bach ,  Peter Brandl ,  Andrew Christopher Graeme Wood

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L21/266 ,  H01L21/225 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor component includes a field-effect transistor arrangement having a drift zone and body region between the drift zone and a first surface of a semiconductor body. Trench structures of a first type extend from the first surface into the semiconductor body and have a maximum lateral dimension at the first surface which is less than a depth of first and second ones of the trench structures. A net doping concentration at a reference depth at a first location in the drift zone is at least 10% greater than at a second location in the drift zone at the reference depth, which is located between the body region and a bottom of the first trench structure. The first location is at the same first lateral distance from the first and second trench structures. The second location is at the same second lateral distance from the first and second trench structures.

公开(公告)号：US20180114788A1

公开(公告)日：2018-04-26

申请号：US15792492

申请日：2017-10-24

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0292 ,  H01L27/0255 ,  H01L27/0288 ,  H01L27/0296 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/78618 ,  H01L29/8083

Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

公开(公告)号：US20150115356A1

公开(公告)日：2015-04-30

申请号：US14067065

申请日：2013-10-30

Applicant: Infineon Technologies AG

Inventor： Peter Brandl ,  Matthias Hermann Peri

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L21/31 ,  H01L21/265 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/324 ,  H01L27/088 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: Producing a vertical semiconductor device includes: providing a semiconductor wafer including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type forming a first pn-junction with the first layer, and a third semiconductor layer of the first conductivity type forming a second pn-junction with the second layer and extending to a main surface of the wafer; forming a hard mask on the main surface that includes hard mask portions spaced apart from each other by first openings; using the hard mask to etch deep trenches from the main surface into the first layer so that mesa regions covered at the main surface by respective hard mask portions are formed between adjacent trenches; filling the trenches and first openings of the hard mask; and etching the hard mask to form second openings in the hard mask at the main surface of the mesas.

Abstract translation: 制造垂直半导体器件包括：提供包括第一导电类型的第一半导体层，与第一层形成第一pn结的第二导电类型的第二半导体层和第一半导体层的第三半导体层的半导体晶片 导电类型与第二层形成第二pn结并延伸到晶片的主表面; 在主表面上形成硬掩模，其包括通过第一开口彼此间隔开的硬掩模部分; 使用硬掩模将深沟槽从主表面蚀刻到第一层中，使得通过相应的硬掩模部分在主表面处覆盖的台面区域形成在相邻的沟槽之间; 填充硬掩模的沟槽和第一开口; 并且蚀刻硬掩模以在台面的主表面处在硬掩模中形成第二开口。

公开(公告)号：US20150097233A1

公开(公告)日：2015-04-09

申请号：US14045925

申请日：2013-10-04

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Peter Brandl

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7815

Abstract: A semiconductor device includes a vertical IGFET in a first area of a semiconductor body, the vertical IGFET having a drift zone between a body zone and a drain electrode, the drift zone having a vertical dopant profile of a first conductivity type being a superposition of a first dopant profile declining with increasing distance from the drain electrode and dominating the vertical dopant profile in a first zone next to the drain electrode and a second dopant profile being a broadened peak dopant profile and dominating the vertical dopant profile in a second zone next to the body zone.

Abstract translation: 半导体器件包括在半导体本体的第一区域中的垂直IGFET，垂直IGFET具有在体区和漏极之间的漂移区，漂移区具有第一导电类型的垂直掺杂剂分布， 第一掺杂剂分布随着与漏极电极的距离增加而下降，并且在靠近漏电极的第一区域中支配垂直掺杂剂分布，第二掺杂剂分布是扩展的峰值掺杂物分布，并且在邻近的第二区域中支配垂直掺杂剂分布 身体区域。