公开(公告)号：US20190198650A1

公开(公告)日：2019-06-27

申请号：US16289166

申请日：2019-02-28

Applicant: Infineon Technologies AG

Inventor： Thomas WUEBBEN ,  Peter IRSIGLER ,  Hans-Joachim SCHULZE

IPC: H01L29/739 ,  H01L21/266 ,  H01L21/265 ,  H01L21/225 ,  H01L21/223 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L21/2236 ,  H01L21/2252 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.

公开(公告)号：US20170117395A1

公开(公告)日：2017-04-27

申请号：US15295109

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Thomas WUEBBEN ,  Peter IRSIGLER ,  Hans-Joachim SCHULZE

IPC: H01L29/739 ,  H01L29/06 ,  H01L21/265 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L21/2236 ,  H01L21/2252 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.

公开(公告)号：US20180175150A1

公开(公告)日：2018-06-21

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton MAUDER ,  Oliver HELLMUND ,  Peter IRSIGLER ,  Jens Peter KONRATH ,  David LAFORET ,  Maik LANGNER ,  Markus NEUBER ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC ,  Knut STAHRENBERG ,  Olaf STORBECK

IPC: H01L29/16 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US20170031239A1

公开(公告)日：2017-02-02

申请号：US15220480

申请日：2016-07-27

Applicant: Infineon Technologies AG

Inventor： Sebastian SCHMIDT ,  Martina SEIDER-SCHMIDT ,  Peter IRSIGLER ,  Oliver HELLMUND

IPC: G03F1/50 ,  G03F7/16 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F1/50 ,  G03F1/70 ,  G03F7/0035 ,  H01L21/0274 ,  H01L21/32139

Abstract: In various embodiments, a reticle is provided. The reticle may include a feature. The feature may include a base structure, and a step structure. The a step structure includes a center region and an edge region. The center region includes, in a top view, a larger width than the edge region. The step structure is configured to be arranged over a topography step of a substrate to be lithographically processed.

Abstract translation: 在各种实施例中，提供了掩模版。 掩模版可以包括特征。 该特征可以包括基础结构和阶梯结构。 该台阶结构包括中心区域和边缘区域。 中心区域在顶视图中包括比边缘区域更大的宽度。 台阶结构被配置为布置在待光刻处理的基板的地形台阶上。