公开(公告)号：US20150364550A1

公开(公告)日：2015-12-17

申请号：US14306071

申请日：2014-06-16

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim SCHULZE ,  Jens Peter KONRATH ,  Roland RUPP ,  Christian HECHT

IPC: H01L29/16 ,  H01L21/02

CPC classification number: H01L29/1608 ,  H01L21/0465 ,  H01L21/26506 ,  H01L21/762 ,  H01L21/76254 ,  H01L29/7395 ,  H01L29/7827

Abstract: Representative implementations of devices and techniques provide an optimized layer for a semiconductor component. In an example, a doped portion of a wafer, forming a substrate layer may be transferred from the wafer to an acceptor, or handle wafer. A component layer may be applied to the substrate layer. The acceptor wafer is detached from the substrate layer. In some examples, further processing may be executed with regard to the substrate and/or component layers.

Abstract translation: 器件和技术的代表性实现为半导体部件提供优化的层。 在一个示例中，形成衬底层的晶片的掺杂部分可以从晶片转移到受主或处理晶片。 组分层可以施加到基底层。 受主晶片与衬底层分离。 在一些示例中，可以针对衬底和/或组件层执行进一步的处理。

公开(公告)号：US20200219972A1

公开(公告)日：2020-07-09

申请号：US16733329

申请日：2020-01-03

Applicant: Infineon Technologies AG

Inventor： Caspar LEENDERTZ ,  Rudolf ELPELT ,  Romain ESTEVE ,  Thomas GANNER ,  Jens Peter KONRATH ,  Larissa WEHRHAHN-KILIAN

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/47

Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.

公开(公告)号：US20180175150A1

公开(公告)日：2018-06-21

申请号：US15848707

申请日：2017-12-20

Applicant: Infineon Technologies AG

Inventor： Anton MAUDER ,  Oliver HELLMUND ,  Peter IRSIGLER ,  Jens Peter KONRATH ,  David LAFORET ,  Maik LANGNER ,  Markus NEUBER ,  Hans-Joachim SCHULZE ,  Ralf SIEMIENIEC ,  Knut STAHRENBERG ,  Olaf STORBECK

IPC: H01L29/16 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02

Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.

公开(公告)号：US20160155714A1

公开(公告)日：2016-06-02

申请号：US14555736

申请日：2014-11-28

Applicant: Infineon Technologies AG

Inventor： Jochen HILSENBECK ,  Jens Peter KONRATH ,  Thomas FRANK ,  Roland RUPP

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3121 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/4238 ,  H01L29/43 ,  H01L29/7392 ,  H01L29/7396 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/8083 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/45124 ,  H01L2924/01014 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/3512

Abstract: According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

Abstract translation: 根据各种实施例，半导体器件可以包括：形成在半导体器件的表面处的层堆叠，所述层堆叠包括：包括第一金属或金属合金的金属化层; 覆盖金属化层的保护层，保护层包括第二金属或金属合金，其中第二金属或金属合金比第一金属或金属合金低。

公开(公告)号：US20240105832A1

公开(公告)日：2024-03-28

申请号：US18371620

申请日：2023-09-22

Applicant: Infineon Technologies AG

Inventor： Thomas Ralf SIEMIENIEC ,  Hans-Joachim SCHULZE ,  Jens Peter KONRATH

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7811 ,  H01L21/045 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068

Abstract: A field effect transistor (FET) is proposed. The FET includes a transistor cell area in a silicon carbide (SiC) semiconductor body. An edge termination area surrounds the transistor cell area. A source contact is arranged over a first surface of the SiC semiconductor body. A drain contact is arranged on a second surface of the SiC semiconductor body. The FET further includes a drift region of a first conductivity type between the first surface and the second surface. Along a lateral direction, a net doping concentration in the drift region is larger in the transistor cell area than in the edge termination area.