公开(公告)号：US11848237B2

公开(公告)日：2023-12-19

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/8234 ,  H01L21/561 ,  H01L21/762 ,  H01L21/76873 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49562 ,  H01L25/0655 ,  H01L23/3114 ,  H01L23/3135 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US10672664B2

公开(公告)日：2020-06-02

申请号：US16081236

申请日：2017-02-27

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/78 ,  H01L21/8234 ,  H01L21/56 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

公开(公告)号：US20210143108A1

公开(公告)日：2021-05-13

申请号：US17071022

申请日：2020-10-15

Applicant: Infineon Technologies AG

Inventor： Christian Gruber ,  Benjamin Bernard ,  Tobias Polster ,  Carsten von Koblinski

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L23/538

Abstract: A semiconductor device includes a semiconductor die having a front side surface, a backside surface opposite the front side surface and side faces. A backside metallization layer is deposited over the backside surface and projects laterally outwards beyond the side faces. A side face protection layer covers the side faces.

公开(公告)号：US20200273750A1

公开(公告)日：2020-08-27

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

公开(公告)号：US20230187381A1

公开(公告)日：2023-06-15

申请号：US18106028

申请日：2023-02-06

Applicant: Infineon Technologies AG

Inventor： Christian Gruber ,  Benjamin Bernard ,  Tobias Polster ,  Carsten von Koblinski

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/5386

Abstract: A method of manufacturing a semiconductor device includes: forming grooves in a front side surface of a wafer; filling the grooves with a first side face protection material; thinning the wafer at a backside surface of the wafer opposite the front side surface; depositing a backside metallization layer over the backside surface of the thinned wafer; and laser cutting along the grooves through the side face protection material and through the backside metallization layer to separate the wafer into multiple semiconductor devices.

公开(公告)号：US11605599B2

公开(公告)日：2023-03-14

申请号：US17071022

申请日：2020-10-15

Applicant: Infineon Technologies AG

Inventor： Christian Gruber ,  Benjamin Bernard ,  Tobias Polster ,  Carsten von Koblinski

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die having a front side surface, a backside surface opposite the front side surface and side faces. A backside metallization layer is deposited over the backside surface and projects laterally outwards beyond the side faces. A side face protection layer covers the side faces.

公开(公告)号：US11302579B2

公开(公告)日：2022-04-12

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

公开(公告)号：US12094837B2

公开(公告)日：2024-09-17

申请号：US18106028

申请日：2023-02-06

Applicant: Infineon Technologies AG

Inventor： Christian Gruber ,  Benjamin Bernard ,  Tobias Polster ,  Carsten von Koblinski

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/5386

Abstract: A method of manufacturing a semiconductor device includes: forming grooves in a front side surface of a wafer; filling the grooves with a first side face protection material; thinning the wafer at a backside surface of the wafer opposite the front side surface; depositing a backside metallization layer over the backside surface of the thinned wafer; and laser cutting along the grooves through the side face protection material and through the backside metallization layer to separate the wafer into multiple semiconductor devices.

公开(公告)号：US20220181211A1

公开(公告)日：2022-06-09

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US11322400B2

公开(公告)日：2022-05-03

申请号：US16906586

申请日：2020-06-19

Applicant: Infineon Technologies AG

Inventor： Carsten von Koblinski ,  Tobias Polster

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528

Abstract: A method of manufacturing a semiconductor wafer having a roughened metallization layer surface is described. The method includes immersing the semiconductor wafer in an electrolytic bath. Gas bubbles are generated in the electrolytic bath. A surface of a metallization layer on the semiconductor wafer is electrochemically roughened in the presence of the gas bubbles by applying a reversing voltage between the metallization layer and an electrode of the electrolytic bath.