公开(公告)号：US20200273750A1

公开(公告)日：2020-08-27

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

公开(公告)号：US10121859B2

公开(公告)日：2018-11-06

申请号：US15457833

申请日：2017-03-13

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Oliver Blank ,  Oliver Hellmund ,  Martin Poelzl

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/78 ,  H01L21/68 ,  H01L21/683 ,  B81B7/00 ,  B81C1/00 ,  H01L29/40 ,  H01L29/78

Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

公开(公告)号：US20160233308A1

公开(公告)日：2016-08-11

申请号：US15098789

申请日：2016-04-14

Applicant: Infineon Technologies AG

Inventor： Andrew Christopher Graeme Wood ,  Oliver Blank ,  Martin Poelzl ,  Martin Vielemeyer

IPC: H01L29/40 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L27/0629 ,  H01L27/11526 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8605 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body, having a first surface, a gate electrode structure, which includes polycrystalline silicon, of an IGFET in a first trench extending from the first surface into the semiconductor body. The device also includes a semiconductor element, which is different from the gate electrode structure of the IGFET and includes polycrystalline silicon, in a second trench extending from the first surface into the semiconductor body, wherein the polycrystalline silicon of the IGFET and of the semiconductor element different therefrom ends below a top side of an insulation layer adjoining the first surface of the semiconductor body.

Abstract translation: 半导体器件包括半导体本体，其具有第一表面，包括多晶硅的栅极电极结构，所述第一表面包括多晶硅，所述第一表面在从所述第一表面延伸到所述半导体本体中的第一沟槽中具有IGFET。 所述器件还包括半导体元件，所述半导体元件与所述IGFET的栅电极结构不同，并且在从所述第一表面延伸到所述半导体本体的第二沟槽中包括多晶硅，其中所述IGFET的多晶硅和所述半导体元件 不同之处在与半导体本体的第一表面相邻的绝缘层的顶侧下方。

公开(公告)号：US09306058B2

公开(公告)日：2016-04-05

申请号：US14043971

申请日：2013-10-02

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/2822 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825

Abstract: An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

Abstract translation: 集成电路包括具有主表面的半导体衬底中的晶体管。 晶体管包括源极区，漏极区，沟道区，漂移区，栅电极和与栅电极相邻的栅极电介质。 栅电极设置成与沟道区域的至少两侧相邻。 沟道区域和漂移区域沿着平行于源极区域和漏极区域之间的主表面的第一方向设置。 栅极电介质具有在栅电极的不同位置处变化的厚度。

公开(公告)号：US20210183763A1

公开(公告)日：2021-06-17

申请号：US17170359

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.

公开(公告)号：US10971449B2

公开(公告)日：2021-04-06

申请号：US16722734

申请日：2019-12-20

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213 ,  H01L23/31 ,  H01L29/40 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

公开(公告)号：US10593623B2

公开(公告)日：2020-03-17

申请号：US15804396

申请日：2017-11-06

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/31 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

公开(公告)号：US10355087B2

公开(公告)日：2019-07-16

申请号：US15062370

申请日：2016-03-07

Applicant: Infineon Technologies AG

Inventor： Martin Vielemeyer ,  Andreas Meiser ,  Till Schloesser ,  Franz Hirler ,  Martin Poelzl

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L21/265

Abstract: A semiconductor device includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode.

公开(公告)号：US09754859B2

公开(公告)日：2017-09-05

申请号：US14037057

申请日：2013-09-25

Applicant: Infineon Technologies AG

Inventor： Walter Rieger ,  Franz Hirler ,  Martin Poelzl ,  Manfred Kotek

IPC: H01L29/732 ,  H01L23/48 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, a doped zone, a polysilicon layer and an elongate plug structure. The doped zone is within the semiconductor substrate. The polysilicon layer is disposed in a trench electrically isolated from the semiconductor substrate by an insulating layer. The elongate plug structure extends in a lateral direction in or above the semiconductor substrate. The elongate plug structure provides electrical connection between the doped zone and the polysilicon layer.

公开(公告)号：US11552016B2

公开(公告)日：2023-01-10

申请号：US17170359

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/31 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.