公开(公告)号：US20210057375A1

公开(公告)日：2021-02-25

申请号：US16991123

申请日：2020-08-12

Applicant: Infineon Technologies AG

Inventor： Wee Aun Jason Lim ,  Paul Armand Asentista Calo ,  Ting Soon Chin ,  Chooi Mei Chong ,  Sanjay Kumar Murugan ,  Ying Pok Sam ,  Chee Voon Tan

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

公开(公告)号：US11239127B2

公开(公告)日：2022-02-01

申请号：US16906617

申请日：2020-06-19

Applicant: Infineon Technologies AG

Inventor： Edward Myers ,  Liu Chen ,  Chee Chiew Chong ,  Wee Aun Jason Lim ,  Wee Boon Tay

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

公开(公告)号：US20240087993A1

公开(公告)日：2024-03-14

申请号：US17944657

申请日：2022-09-14

Applicant: Infineon Technologies AG

Inventor： Wee Aun Jason Lim ,  Marie Hazel Barozzo Gabrillo ,  Chai Chee Lee ,  Nor Haqimi Mohamed

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49548 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49517 ,  H01L24/32 ,  H01L2224/32245

Abstract: A molded package includes: a semiconductor die; a substrate attached to a bottom side of the semiconductor die; an electrically conductive clip attached to a top side of the semiconductor die; and a mold compound encapsulating the semiconductor die. A top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound. A bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die. Along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface. A method of producing the molded package is also described.

公开(公告)号：US11211356B2

公开(公告)日：2021-12-28

申请号：US16991123

申请日：2020-08-12

Applicant: Infineon Technologies AG

Inventor： Wee Aun Jason Lim ,  Paul Armand Asentista Calo ,  Ting Soon Chin ,  Chooi Mei Chong ,  Sanjay Kumar Murugan ,  Ying Pok Sam ,  Chee Voon Tan

IPC: H01L23/495 ,  H01L23/28 ,  H01L21/00 ,  H05K7/18 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.