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    INTERCONNECT CLIP FOR VERTICALLY STACKED DIE ARRANGEMENT
    1.
    发明申请
    INTERCONNECT CLIP FOR VERTICALLY STACKED DIE ARRANGEMENT 有权

    公开(公告)号：US20250096082A1

    公开(公告)日：2025-03-20

    申请号：US18369443

    申请日：2023-09-18

    Applicant: Infineon Technologies AG

    Inventor： Mei Yih Goh ,  Chee Voon Tan ,  Sung Hoe Yeong ,  Michael Stadler

    IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07

    Abstract: An electrical interconnect clip includes a die interface portion that is adapted for mating in between two vertically stacked semiconductor dies, and a carrier connection portion that is configured to electrically connect the two vertically stacked semiconductor dies with a carrier, wherein the die interface portion comprises a lower mating surface, an upper mating surface opposite from the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface that are spaced apart from the outer edge sides of the electrical interconnect clip and surround a die attach area of the upper mating surface.

    Double-sided cooled molded semiconductor package
    3.
    发明授权
    Double-sided cooled molded semiconductor package 有权

    公开(公告)号：US11302613B2

    公开(公告)日：2022-04-12

    申请号：US16924851

    申请日：2020-07-09

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Swee Kah Lee ,  Josef Maerz ,  Thomas Stoek ,  Chee Voon Tan

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/18

    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.

    Semiconductor Package with Lead Tip Inspection Feature
    6.
    发明申请
    Semiconductor Package with Lead Tip Inspection Feature 有权

    公开(公告)号：US20210366732A1

    公开(公告)日：2021-11-25

    申请号：US16882008

    申请日：2020-05-22

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Khay Chwan Andrew Saw ,  Chee Voon Tan

    IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538

    Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device. The sidewall-facing terminal of each packaged semiconductor device is provided from the electrically conductive material formed within the gaps.

    Molded semiconductor package with double-sided cooling
    7.
    发明授权
    Molded semiconductor package with double-sided cooling 有权

    公开(公告)号：US10886199B1

    公开(公告)日：2021-01-05

    申请号：US16514115

    申请日：2019-07-17

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Swee Kah Lee ,  Josef Maerz ,  Thomas Stoek ,  Chee Voon Tan

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L23/18

    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

    Molded Semiconductor Package with Double-Sided Cooling
    9.
    发明申请
    Molded Semiconductor Package with Double-Sided Cooling 有权

    公开(公告)号：US20210020547A1

    公开(公告)日：2021-01-21

    申请号：US16514115

    申请日：2019-07-17

    Applicant: Infineon Technologies AG

    Inventor： Chau Fatt Chiang ,  Swee Kah Lee ,  Josef Maerz ,  Thomas Stoek ,  Chee Voon Tan

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/29

    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

    Semiconductor Device Having Multiple Chips Mounted to a Carrier
    10.
    发明申请
    Semiconductor Device Having Multiple Chips Mounted to a Carrier 有权
    具有安装到载体的多个芯片的半导体器件

    公开(公告)号：US20150249067A1

    公开(公告)日：2015-09-03

    申请号：US14193897

    申请日：2014-02-28

    Applicant: Infineon Technologies AG

    Inventor： Boon Seong Lee ,  Chee Voon Tan

    IPC: H01L25/065 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier.

    Abstract translation: 半导体器件包括具有第一表面和与第一表面相对的第二表面的芯片载体。 该装置还包括安装在芯片载体的第一表面上的第一半导体芯片。 第二半导体芯片安装在芯片载体的第二表面上，其中面向芯片载体的第二半导体芯片的第一表面的一部分突出在芯片载体的边缘上。 第一电导体耦合到形成在第二半导体芯片的第一表面的在芯片载体的边缘上突出的部分上的电极。

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