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1.发明申请Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts 审中-公开用于DRAM阵列和栅极互连的改进的顶部氧化物层，同时提供自对准栅极触点的可扩展工艺公开(公告)号：US20040256651A1
公开(公告)日：2004-12-23
申请号：US10896547
申请日：2004-07-22
发明人： Thomas W. Dyer , Andreas Knorr , Laertis Economikos , Scott Halle , Rajeev Malik , Norbert Arnold
IPC分类号： H01L029/76 , H01L021/8242 , H01L031/119 , H01L029/94 , H01L021/336
CPC分类号： H01L27/10864 , H01L27/10891
摘要： A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride remaining in place. Once the devices have been formed and the gate polysilicon has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide fills the regions between and on top of the polysilicon plugs. The Top Oxide is then planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.
摘要翻译： 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成垂直装置而形成，其中衬垫氮化物保持就位。 一旦器件已经形成并且栅极多晶硅已经被平坦化到衬底氮化物的表面之下，衬垫氮化物被剥离掉，留下栅极多晶硅插塞的顶部延伸到活性硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物填充多晶硅插塞之间和之上的区域。 然后将顶部氧化物平面化回多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。
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公开(公告)号：US20020155654A1
公开(公告)日：2002-10-24
申请号：US09837799
申请日：2001-04-18
IPC分类号： H01L021/8238
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10888
摘要： A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.
摘要翻译： 存储单元的方法具有沟槽电容器和与电容器相邻的垂直晶体管。 垂直晶体管在沟槽电容器上方具有栅极导体。 栅极导体的上部比栅极导体的下部窄。 存储单元还包括邻近栅极导体的上部的间隔物和邻近栅极导体的位线接触。 间隔物减少了位线接触和栅极导体之间的短路。 栅极导体上方的栅极接触具有将栅极接触与位线分离的绝缘体。 栅极导体的上部和下部的宽度之间的差异减小了位线接触和栅极导体之间的短路。
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公开(公告)号：US20040135188A1
公开(公告)日：2004-07-15
申请号：US10341187
申请日：2003-01-13
发明人： Giuseppe La Rosa , Thomas W. Dyer , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens , Alvin W. Strong
IPC分类号： H01L027/108
CPC分类号： H01L29/945 , H01L27/10861 , H01L27/10894 , H01L29/66181
摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.
摘要翻译： 基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。 该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。
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4.发明申请公开(公告)号：US20040129942A1
公开(公告)日：2004-07-08
申请号：US10337014
申请日：2003-01-03
IPC分类号： H01L027/108 , H01L029/04 , H01L029/76 , H01L029/94 , H01L031/036
CPC分类号： H01L27/10867
摘要： A simple method of forming the buried strap in a trench DRAM sets the separation between the buried strap and the vertical transistor channel by control of the overetch in forming a recess of the buried strap material, instead of setting the separation by the thickness of the trench top oxide.
摘要翻译： 在沟槽DRAM中形成掩埋带的简单方法通过在形成掩埋带材料的凹部中控制过蚀刻来设置掩埋带和垂直晶体管通道之间的间隔，而不是将间隔设置为沟槽的厚度 顶部氧化物。
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公开(公告)号：US20040155275A1
公开(公告)日：2004-08-12
申请号：US10775441
申请日：2004-02-10
IPC分类号： H01L027/108
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.
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6.发明申请公开(公告)号：US20040106258A1
公开(公告)日：2004-06-03
申请号：US10720490
申请日：2003-11-24
IPC分类号： H01L021/8242 , H01L021/336
CPC分类号： H01L27/10864 , H01L21/31612 , H01L21/3185 , H01L27/10867
摘要： A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.
摘要翻译： 在垂直MOSFET DRAM单元器件形成期间，能够在沟槽顶氧化物TTO（高密度等离子体）HDP沉积之前沉积薄氮化物衬垫的结构和方法。 随后在TTO侧壁蚀刻之后移除该衬垫。 该衬垫的一个功能是在TTO氧化物侧壁蚀刻期间保护套环氧化物不被蚀刻，并且通常提供在当前处理方案中未实现的横向蚀刻保护。 工艺顺序不依赖于先前沉积的膜用于套环保护，并且将TTO侧壁蚀刻保护与先前的处理步骤分离，以提供附加的工艺灵活性，例如在节点氮化物去除期间允许更薄的带切割掩模氮化物和更大的氮化物蚀刻和掩埋带 氮化界面去除。 有利地，在TTO之下的氮化物衬垫的存在降低了垂直MOSFET DRAM单元的栅极和电容器节点电极之间的TTO介质击穿的可能性，同时确保带扩散到栅极导体重叠。
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