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    Method for multi-depth trench isolation
    1.
    发明申请
    Method for multi-depth trench isolation 失效
    多深度沟槽隔离方法

    公开(公告)号：US20030077875A1

    公开(公告)日：2003-04-24

    申请号：US10004152

    申请日：2001-10-24

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni

    IPC分类号： H01L021/76 ,  H01L021/461

    CPC分类号： H01L21/76229 ,  H01L21/308

    摘要： A method for forming multi-depth apertures in a substrate is provided. The method includes first providing a pad stack atop a surface of a substrate having regions for forming apertures therein, the pad stack includes at least a top patterned masking layer. Next, at least one of the regions of the substrate is blocked with a first block mask, while leaving at least one other region of the substrate unblocked. A plurality of first apertures having a first depth is then formed in the unblocked region of the substrate using the patterned masking layer to define the plurality of first apertures. The first block mask is then removed; and thereafter a plurality of second apertures having a second depth is formed in regions of the substrate that were previously blocked by the first block mask using the same patterned masking layer to define the second apertures, while simultaneously increasing the first depth such that the first depth is deeper than the second depth.

    摘要翻译： 提供了一种在衬底中形成多深度孔的方法。 该方法包括首先在具有用于在其中形成孔的区域的基底的表面顶部提供衬垫叠层，所述衬垫堆叠至少包括顶部图案化掩模层。 接下来，衬底的至少一个区域用第一块掩模阻挡，同时留下衬底的至少一个其它区域被阻挡。 然后使用图案化的掩模层在衬底的未阻挡区域中形成具有第一深度的多个第一孔，以限定多个第一孔。 然后删除第一个块掩码; 此后，在衬底的预先被第一块掩模阻挡的区域中形成具有第二深度的多个第二孔，使用相同的图案化掩模层来限定第二孔，同时增加第一深度使得第一深度 比第二深度更深。

    Gate prespacers for high density, high performance drams
    2.
    发明申请
    Gate prespacers for high density, high performance drams 审中-公开
    门前提供高密度，高性能的drams

    公开(公告)号：US20010054729A1

    公开(公告)日：2001-12-27

    申请号：US09916933

    申请日：2001-07-27

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Ramachandra Divakaruni ,  James William Adkisson ,  Mary Elizabeth Weybright ,  Scott Halle ,  Jeffrey Peter Gambino ,  Heon Lee

    IPC分类号： H01L021/8242 ,  H01L021/8238 ,  H01L021/336 ,  H01L027/108 ,  H01L029/76

    CPC分类号： H01L27/10894 ,  H01L21/823462 ,  H01L27/10873

    摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.

    摘要翻译： 提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。 具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层 形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层 所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及 所述导体材料层上的氮化物覆盖层，所述多晶硅层 形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

    Self-aligned STI for narrow trenches
    3.
    发明申请
    Self-aligned STI for narrow trenches 有权

    公开(公告)号：US20040113230A1

    公开(公告)日：2004-06-17

    申请号：US10722353

    申请日：2003-11-25

    申请人： International Business Machines Corporation

    发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L021/336 ,  H01L029/00

    CPC分类号： H01L27/10867 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/0207 ,  H01L27/10864

    摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.

    STRUCTURE AND METHOD OF FABRICATING EMBEDDED DRAM HAVING A VERTICAL DEVICE ARRAY AND A BORDERED BITLINE CONTACT
    4.
    发明申请
    STRUCTURE AND METHOD OF FABRICATING EMBEDDED DRAM HAVING A VERTICAL DEVICE ARRAY AND A BORDERED BITLINE CONTACT 有权
    具有垂直设备阵列和边界位线接触的嵌入式DRAM的结构和方法

    公开(公告)号：US20040036100A1

    公开(公告)日：2004-02-26

    申请号：US10227404

    申请日：2002-08-23

    申请人： International Business Machines Corporation

    发明人： Ramachandra Divakaruni ,  Babar Ali Khan ,  Carl John Radens

    IPC分类号： H01L021/8242

    CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

    摘要： An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell-further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.

    摘要翻译： 本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体 沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元还包括从晶体管沟道延伸的有源区，以及与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

    Modified vertical MOSFET and methods of formation thereof
    6.
    发明申请
    Modified vertical MOSFET and methods of formation thereof 失效

    公开(公告)号：US20030001200A1

    公开(公告)日：2003-01-02

    申请号：US09896741

    申请日：2001-06-29

    申请人： International Business Machines Corporation

    发明人： Ramachandra Divakaruni ,  Prakash C. Dev ,  Rajeev Malik ,  Larry Nesbit

    IPC分类号： H01L021/336 ,  H01L029/76 ,  H01L029/94

    CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891

    摘要： The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

    Modified gate processing for optimized difinition of array and logic devices on same chip
    7.
    发明申请
    Modified gate processing for optimized difinition of array and logic devices on same chip 失效
    改进的栅极处理，用于在同一芯片上优化阵列和逻辑器件的差异

    公开(公告)号：US20020111025A1

    公开(公告)日：2002-08-15

    申请号：US10117869

    申请日：2002-04-08

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

    IPC分类号： H01L021/302 ,  H01L021/461

    CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

    摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

    摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

    Self-aligned near surface strap for high density trench drams
    8.
    发明申请
    Self-aligned near surface strap for high density trench drams 失效
    自对准近表面带，用于高密度沟渠

    公开(公告)号：US20020079528A1

    公开(公告)日：2002-06-27

    申请号：US10045499

    申请日：2002-01-14

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION AND INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION

    发明人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

    IPC分类号： H01L027/108 ,  H01L029/76

    CPC分类号： H01L27/10867

    摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

    摘要翻译： 一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。 沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。 控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。 此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。 唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。 衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形 形结构。 此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。