公开(公告)号：US20170062276A1

公开(公告)日：2017-03-02

申请号：US15249008

申请日：2016-08-26

申请人： Infineon Technologies Dresden GmbH

发明人： Stefan Tegen ,  Martin Bartels ,  Thomas Bertrams ,  Marko Lemke ,  Rolf Weis

IPC分类号： H01L21/768 ,  H01L29/40 ,  H01L23/535 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L21/76897 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

摘要： A layer stack is formed on a main surface of a semiconductor layer, wherein the layer stack includes a dielectric capping layer and a metal layer between the capping layer and the semiconductor layer. Second portions of the layer stack are removed to form gaps between remnant first portions. Adjustment structures of a second dielectric material are formed in the gaps. An interlayer of the first or a third dielectric material is formed that covers the adjustment structures and the first portions. Contact trenches are formed that extend through the interlayer and the capping layer to metal structures formed from remnant portions of the metal layer in the first portions, wherein the capping layer is etched selectively against the auxiliary structures.

摘要翻译： 在半导体层的主表面上形成层叠体，其中层叠层包括介电覆盖层和覆盖层与半导体层之间的金属层。 去除层堆叠的第二部分以在剩余的第一部分之间形成间隙。 在间隙中形成第二电介质材料的调整结构。 形成了覆盖调整结构和第一部分的第一或第三介电材料的中间层。 形成接触沟槽，其延伸穿过中间层和覆盖层到由第一部分中的金属层的残余部分形成的金属结构，其中覆盖层被选择性地蚀刻到辅助结构上。

公开(公告)号：US09368408B2

公开(公告)日：2016-06-14

申请号：US14141839

申请日：2013-12-27

申请人： Infineon Technologies Dresden GmbH

发明人： Stefan Tegen ,  Marko Lemke ,  Rolf Weis

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8236 ,  H01L27/088

CPC分类号： H01L21/30608 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/8236 ,  H01L27/0883 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion. A channel/body zone is formed in a transistor fin that extends between the first and second electrode fins at a distance to the first surface. The first and second electrode fins extend along a first lateral direction. A width of first gate sections, which are arranged on opposing sides of the transistor fin, along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins.

摘要翻译： 半导体器件包括形成在从第一表面延伸到半导体部分的第一电极片中的第一导电类型的源极区域。 第一导电类型的漏区形成在从第一表面延伸到半导体部分的第二电极翅片中。 通道/体区形成在晶体管翅片上，该晶体管鳍片在第一和第二电极翅片之间延伸到第一表面一定距离处。 第一和第二电极翅片沿着第一横向方向延伸。 沿着垂直于第一横向的第二横向方向布置在晶体管鳍片的相对侧上的第一栅极部分的宽度大于第一和第二电极片之间的距离。

公开(公告)号：US09276107B2

公开(公告)日：2016-03-01

申请号：US14613438

申请日：2015-02-04

申请人： Infineon Technologies Dresden GmbH

发明人： Marko Lemke ,  Rolf Weis ,  Stefan Tegen

IPC分类号： H01L29/792 ,  H01L29/94 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66734 ,  H01L29/78

摘要： A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure.

摘要翻译： 半导体器件包括第一和第二栅电极结构和连接插头。 第一栅极电极结构被埋在半导体部分中，并且在晶体管单元的第一单元阵列内部具有阵列条纹，并且在第一单元阵列外部具有接触条纹，接触条纹与阵列条纹结构地连接。 第二栅极电极结构被埋在半导体部分中，并且在晶体管单元的第二单元阵列内部具有阵列条纹。 半导体部分的阵列隔离区域分离第一和第二栅电极结构。 连接插头在半导体部分的第一表面和第一栅电极结构的接触条之间延伸。

公开(公告)号：US20150145029A1

公开(公告)日：2015-05-28

申请号：US14613438

申请日：2015-02-04

申请人： Infineon Technologies Dresden GmbH

发明人： Marko Lemke ,  Rolf Weis ,  Stefan Tegen

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66734 ,  H01L29/78

摘要： A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure.

摘要翻译： 半导体器件包括第一和第二栅电极结构和连接插头。 第一栅极电极结构被埋在半导体部分中，并且在晶体管单元的第一单元阵列内部具有阵列条纹，并且在第一单元阵列外部具有接触条纹，接触条纹与阵列条纹结构地连接。 第二栅极电极结构被埋在半导体部分中并且在晶体管单元的第二单元阵列内部具有阵列条纹。 半导体部分的阵列隔离区域分离第一和第二栅电极结构。 连接插头在半导体部分的第一表面和第一栅电极结构的接触条之间延伸。

公开(公告)号：US20180212031A1

公开(公告)日：2018-07-26

申请号：US15925192

申请日：2018-03-19

申请人： Infineon Technologies Dresden GmbH

发明人： Rolf Weis ,  Martin Bartels ,  Marko Lemke ,  Stefan Tegen

IPC分类号： H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L21/743 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66696 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7825

摘要： A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer.

公开(公告)号：US09941375B2

公开(公告)日：2018-04-10

申请号：US15417436

申请日：2017-01-27

申请人： Infineon Technologies Dresden GmbH

发明人： Rolf Weis ,  Martin Bartels ,  Marko Lemke ,  Stefan Tegen

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L21/285 ,  H01L29/66

CPC分类号： H01L29/45 ,  H01L21/28518 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66696 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7825

摘要： A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

公开(公告)号：US09653305B2

公开(公告)日：2017-05-16

申请号：US14953103

申请日：2015-11-27

申请人： Infineon Technologies Dresden GmbH

发明人： Stefan Tegen ,  Marko Lemke ,  Rolf Weis

IPC分类号： H01L21/283 ,  H01L29/808 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L27/088 ,  H01L29/04 ,  H01L21/8234

CPC分类号： H01L21/283 ,  H01L21/823487 ,  H01L27/0883 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8083

摘要： A semiconductor component includes semiconductor fins formed between a base plane and a main surface of a semiconductor body. Each semiconductor fin includes a source region formed between the main surface and a channel/body region, and a drift zone formed between the channel/body region and the base plane. The semiconductor component further includes gate electrode structures on two mutually opposite sides of each channel/body region, and a field electrode structure between mutually adjacent ones of the semiconductor fins. Each field electrode structure is separated from the drift zone by a field dielectric and extends from the main surface as far as the base plane. The gate electrode structures assigned to the mutually adjacent semiconductor fins enclose an upper portion of the corresponding field electrode structure from two sides.

公开(公告)号：US09412601B2

公开(公告)日：2016-08-09

申请号：US13833166

申请日：2013-03-15

申请人： Infineon Technologies Dresden GmbH

发明人： Stefan Tegen ,  Marko Lemke

IPC分类号： H01L21/285 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/66 ,  H01L21/84

CPC分类号： H01L21/823431 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/28506 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795

摘要： A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.

摘要翻译： 一种用于处理载体的方法可以包括：形成多个结构元件，所述结构元件至少在载体中和载体中的一个上，其中所述多个结构元件中的至少两个相邻的结构元件具有彼此之间的第一距离; 在所述多个结构元件上沉积具有等于所述至少两个相邻结构元件之间的第一距离的厚度的第一层; 在所述第一层上形成至少一个附加层，其中所述至少一个附加层覆盖所述第一层的暴露表面; 去除所述至少一个附加层的一部分以部分暴露所述第一层; 并且部分地去除所述第一层，其中所述至少两个相邻结构元件的至少一个侧壁部分地暴露。

公开(公告)号：US20150187654A1

公开(公告)日：2015-07-02

申请号：US14141839

申请日：2013-12-27

申请人： Infineon Technologies Dresden GmbH

发明人： Stefan Tegen ,  Marko Lemke ,  Rolf Weis

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/8236

CPC分类号： H01L21/30608 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/8236 ,  H01L27/0883 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes a source zone of a first conductivity type formed in a first electrode fin that extends from a first surface into a semiconductor portion. A drain region of the first conductivity type is formed in a second electrode fin that extends from the first surface into the semiconductor portion. A channel/body zone is formed in a transistor fin that extends between the first and second electrode fins at a distance to the first surface. The first and second electrode fins extend along a first lateral direction. A width of first gate sections, which are arranged on opposing sides of the transistor fin, along a second lateral direction perpendicular to the first lateral direction is greater than a distance between the first and second electrode fins.

摘要翻译： 半导体器件包括形成在从第一表面延伸到半导体部分的第一电极片中的第一导电类型的源极区域。 第一导电类型的漏区形成在从第一表面延伸到半导体部分的第二电极翅片中。 通道/体区形成在晶体管翅片上，该晶体管鳍片在第一和第二电极翅片之间延伸到第一表面一定距离处。 第一和第二电极翅片沿着第一横向方向延伸。 沿着垂直于第一横向的第二横向方向布置在晶体管鳍片的相对侧上的第一栅极部分的宽度大于第一和第二电极片之间的距离。

公开(公告)号：US20140141602A1

公开(公告)日：2014-05-22

申请号：US14063362

申请日：2013-10-25

申请人： Infineon Technologies Dresden GmbH

发明人： Kurt Sorschag ,  Daniel Sarlette ,  Felix Braun ,  Marcel Heller ,  Dieter Kaiser ,  Ingo Meusel ,  Marko Lemke ,  Anton Mauder ,  Helmut Strack

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/02

CPC分类号： H01L21/30604 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/306 ,  H01L21/311 ,  H01L29/0657 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/66795 ,  H01L29/7827

摘要： A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas extending to an upper side so that adjacent semiconductor mesas are spaced apart from each other by one of a substantially empty trench and a trench substantially filled with a sacrificial layer selectively etchable with respect to the semiconductor mesas; forming a support structure mechanically connecting the semiconductor mesas spaced apart from each other by one of the substantially empty trench and the trench substantially filled with the sacrificial layer; and processing the semiconductor substrate from the upper side while the semiconductor mesas are mechanically connected via the support structure.

摘要翻译： 提供一种半导体器件的制造方法。 该方法包括：在半导体衬底中形成多个延伸到上侧的半导体台面，使得相邻的半导体台面通过基本为空的沟槽和基本上填充有可选择性地可蚀刻的牺牲层的沟槽彼此间隔开 到半导体台面; 形成将所述半导体台面彼此间隔开的支撑结构，所述半透明台面基本上为空的沟槽之一和所述沟槽基本上被所述牺牲层填充; 并且从上侧处理半导体衬底，同时半导体台面通过支撑结构机械连接。