公开(公告)号：US10310588B2

公开(公告)日：2019-06-04

申请号：US15296096

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

公开(公告)号：US09753525B2

公开(公告)日：2017-09-05

申请号：US14581781

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Nazar S. Haider ,  Dean Mulla ,  Allen W. Chu

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/305 ,  Y02D10/152

Abstract: Systems, methods, and devices are disclosed for mitigating voltage droop in a computing device. An example apparatus includes a plurality of threshold registers to store respective voltage droop thresholds, and an interface to receive a license grant message indicating a license mode for a processor core or domain. The license mode corresponds to a selected set of execution units in the processor core or domain. The apparatus also includes a voltage droop correction module to, based on the license mode indicated in the license grant message, select one of the voltage droop thresholds from the plurality of voltage droop registers, and compare a voltage droop in the processor core or domain with the selected voltage droop threshold. Based on the comparison, the apparatus triggers a voltage droop correction process.

公开(公告)号：US20170102752A1

公开(公告)日：2017-04-13

申请号：US15296096

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

公开(公告)号：US09495001B2

公开(公告)日：2016-11-15

申请号：US13972569

申请日：2013-08-21

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3287 ,  G06F1/266 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，耦合到多个核心的功率传递逻辑，以及功率控制器，其包括使第一核心进入第一低功率状态的第一逻辑 在第一核心的至少一个线程的执行期间独立于OS的操作系统电源管理方案。 描述和要求保护其他实施例。