公开(公告)号：US20230197592A1

公开(公告)日：2023-06-22

申请号：US17553189

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Brandon RAWLINGS ,  Aleksandar ALEKSOV ,  Andrew P. COLLINS ,  Georgios C. DOGIAMIS ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/15 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/181

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.

公开(公告)号：US20200219814A1

公开(公告)日：2020-07-09

申请号：US16648640

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: A device package and method of forming the device package are described. The device package includes a dielectric on a conductive pad, a first via on a top surface of conductive pad, where the first via extends through dielectric, and a conductive trace on dielectric. The device package has a second via on dielectric, where the conductive trace connects to first and second vias, and the second via connects to an edge of conductive trace opposite from first via. The device package may have a seed on dielectric, where the seed electrically couples to conductive trace, a first seed on the top surface of conductive pad, where the first via is on first seed, and a second seed on a top surface of first via, the second seed on surfaces of second via, where the conductive trace is on second seed disposed on both first and second vias.

公开(公告)号：US20230197646A1

公开(公告)日：2023-06-22

申请号：US17557948

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Brandon RAWLINGS ,  Andrew P. COLLINS ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/66 ,  H01L23/15 ,  H01L23/498 ,  H01P3/08

CPC classification number: H01L23/66 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01P3/081 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6638

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.

公开(公告)号：US20200294901A1

公开(公告)日：2020-09-17

申请号：US16649578

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L21/48

Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

公开(公告)号：US20200258839A1

公开(公告)日：2020-08-13

申请号：US16648850

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Veronica STRONG ,  Brandon RAWLINGS

IPC: H01L23/538 ,  H01L23/498

Abstract: A device package and a method of forming a device package are described. The device package includes a dielectric on a conductive pad, and a first via on a first seed on a top surface of the conductive pad. The device package further includes a conductive trace on the dielectric, and a second via on a second seed layer on the dielectric. The conductive trace connects to the first via and the second via, where the second via connects to an edge of the conductive trace opposite from the first via. The dielectric may include a photoimageable dielectric or a buildup film. The device package may also include a seed on the dielectric prior to the conductive trace on the dielectric, and a second dielectric on the dielectric, the conductive trace, and the first and second vias, where the second dielectric exposes a top surface of the second via.

公开(公告)号：US20230208010A1

公开(公告)日：2023-06-29

申请号：US17561733

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Veronica STRONG ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Brandon RAWLINGS

IPC: H01Q1/22 ,  H01Q13/10 ,  H01L23/498

CPC classification number: H01Q1/2283 ,  H01Q13/10 ,  H01L23/49822 ,  H05K1/181

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, an electromagnetic wave launcher is embedded in the core. In an embodiment, the electromagnetic wave launcher comprises a fin, where the fin is a conductive material, and where the fin comprises a stepped profile.

公开(公告)号：US20230207493A1

公开(公告)日：2023-06-29

申请号：US17561578

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Aleksandar ALEKSOV ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Brandon RAWLINGS ,  Gerogios C. DOGIAMIS

IPC: H01L23/64 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/15 ,  H01L23/49827

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a magnetic ring is embedded in the substrate. In an embodiment, a loop is around the magnetic ring. In an embodiment, the loop is conductive and comprises a first via through the substrate, a second via through the substrate, and a trace over a surface of the substrate, where the trace electrically couples the first via to the second via.

公开(公告)号：US20230207408A1

公开(公告)日：2023-06-29

申请号：US17561735

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Brandon RAWLINGS ,  Veronica STRONG

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/486 ,  H01L24/16 ,  C03C23/0025

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core. In an embodiment, the core comprises glass. In an embodiment, a blind via is provided into the core. In an embodiment, a plate spans across the blind via.

公开(公告)号：US20230207407A1

公开(公告)日：2023-06-29

申请号：US17561734

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Brandon RAWLINGS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Aleksandar ALEKSOV

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/486 ,  H01L24/16 ,  C03C23/0025

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a via opening is formed through the core. In an embodiment, the via opening has an aspect ratio (depth:width) that is approximately 5:1 or greater. In an embodiment, the electronic package further comprises a via in the via opening, where the via opening is fully filled.

公开(公告)号：US20230197541A1

公开(公告)日：2023-06-22

申请号：US17557913

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Telesphor KAMGAING ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Brandon RAWLINGS ,  Neelam PRABHU GAUNKAR

IPC: H01L23/15 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49816

Abstract: Embodiments disclosed herein include an electronic package that comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass. In an embodiment, the electronic package further comprises an opening through the substrate from the first surface to the second surface, where the opening comprises a first end proximate to the first surface of the substrate, a second end proximate to the second surface of the substrate, and a middle region between the first end and the second end. In an embodiment, the middle region has a discontinuous slope at junctions with the first end and the second end.