公开(公告)号：US20230207405A1

公开(公告)日：2023-06-29

申请号：US17561722

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Arghya SAIN ,  Andrew P. COLLINS ,  Sivaseetharaman PANDI ,  Telesphor KAMGAING ,  Tolga ACIKALIN ,  Shuhei YAMADA

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49822 ,  H01L21/486 ,  H01L24/16 ,  H01L2924/15311 ,  H01L2224/16227

Abstract: Embodiments disclosed herein include electronic devices. In an embodiment, an electronic device comprises a core, where the core comprises a first layer comprising glass, and a second layer comprising glass over the first layer. In an embodiment, a trace is between the first layer and the second layer. In an embodiment, routing layers are on the core.

公开(公告)号：US20230207406A1

公开(公告)日：2023-06-29

申请号：US17561730

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Arghya SAIN ,  Andrew P. COLLINS ,  Sivaseetharaman PANDI ,  Jianyong XIE ,  Telesphor KAMGAING

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.

公开(公告)号：US20230197646A1

公开(公告)日：2023-06-22

申请号：US17557948

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Brandon RAWLINGS ,  Andrew P. COLLINS ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/66 ,  H01L23/15 ,  H01L23/498 ,  H01P3/08

CPC classification number: H01L23/66 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01P3/081 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6638

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.

公开(公告)号：US20230197593A1

公开(公告)日：2023-06-22

申请号：US17553214

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Sivaseetharaman PANDI ,  Andrew P. COLLINS ,  Arghya SAIN ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass, and a first via through the core. In an embodiment, a first fin extends out laterally from the first via. In an embodiment, the electronic package further comprises a second via through the core, and a second fin extending out laterally from the second via. In an embodiment, a face of the first fin overlaps a face of the second fin.

公开(公告)号：US20230097236A1

公开(公告)日：2023-03-30

申请号：US17485287

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Aleksandar ALEKSOV ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Telesphor KAMGAING ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, where the package substrate comprises: a core substrate. In an embodiment, the core substrate comprises glass. In an embodiment, a via passes through the core substrate. In an embodiment, a die is coupled to the package substrate, where the die comprises an IO interface. In an embodiment, the IO interface is electrically coupled to the via and the via is within a footprint of the die.