公开(公告)号：US10056380B2

公开(公告)日：2018-08-21

申请号：US14779936

申请日：2013-06-20

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Salman Latif ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20230282717A1

公开(公告)日：2023-09-07

申请号：US17687032

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Nikhil J. Mehta ,  Krishna Ganesan ,  Chanaka D. Munasinghe ,  Tahir Ghani ,  Charles H. Wallace

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/401

Abstract: Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.

公开(公告)号：US20170125419A1

公开(公告)日：2017-05-04

申请号：US15409435

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66803 ,  H01L29/7851

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20230282575A1

公开(公告)日：2023-09-07

申请号：US17685541

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Chanaka D. Munasinghe ,  Manish Chandhok ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L27/088 ,  H01L21/823475 ,  H01L29/401 ,  H01L29/41775 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/76897

Abstract: An integrated circuit includes (i) a first transistor device having a first source or drain region coupled to a first source or drain contact, and a first gate electrode, (ii) a second transistor device having a second source or drain region coupled to a second source or drain contact, and a second gate electrode, (iii) a first dielectric material above the first and second source or drain contacts, (iv) a second dielectric material above the first and second gate electrodes, (v) a third dielectric material above the first and second dielectric materials, and (vi) an interconnect feature above and conductively coupled to the first source or drain contact. In an example, the interconnect feature comprises an upper body of conductive material extending within the third dielectric material, and a lower body of conductive material extending within the first dielectric material, with an interface between the upper and lower bodies.

公开(公告)号：US10964697B2

公开(公告)日：2021-03-30

申请号：US16812726

申请日：2020-03-09

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Salman Latif ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20200251471A1

公开(公告)日：2020-08-06

申请号：US16853545

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20190287973A1

公开(公告)日：2019-09-19

申请号：US16430203

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L21/225 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US10396079B2

公开(公告)日：2019-08-27

申请号：US16103430

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Salman Latif ,  Chanaka D. Munasinghe

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L27/088 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.