公开(公告)号：US20180308784A1

公开(公告)日：2018-10-25

申请号：US15769705

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Chandra M. JHA ,  Eric LI

IPC: H01L23/433 ,  H01L23/367 ,  H01L23/24 ,  H01L23/31 ,  H01L23/373

Abstract: An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive material and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.

公开(公告)号：US20210183741A1

公开(公告)日：2021-06-17

申请号：US16636296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Chandra M. JHA ,  Je-Young CHANG

IPC: H01L23/473 ,  H01L23/40 ,  H01L23/373

Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.

公开(公告)号：US20200176352A1

公开(公告)日：2020-06-04

申请号：US16612340

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Je-Young CHANG ,  Chandra M. JHA ,  Shankar DEVASENATHIPATHY ,  Feras EID ,  John C. JOHNSON

IPC: H01L23/427 ,  H01L23/26 ,  H01L23/373 ,  H01L23/433 ,  H01L21/48 ,  F28D15/02

Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

公开(公告)号：US20200066655A1

公开(公告)日：2020-02-27

申请号：US16611830

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Venkata Suresh R. GUTHIKONDA ,  Shankar DEVASENATHIPATHY ,  Chandra M. JHA ,  Je-Young CHANG ,  Kyle YAZZIE ,  Prasanna RAGHAVAN ,  Pramod MALATKAR

IPC: H01L23/00 ,  H01L23/544 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065 ,  H01L21/50

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

公开(公告)号：US20190043772A1

公开(公告)日：2019-02-07

申请号：US16075120

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Purushotham Kaushik MUTHUR SRINATH ,  Pramod MALATKAR ,  Sairam AGRAHARAM ,  Chandra M. JHA ,  Arnab CHOUDHURY ,  Nachiket R. RARAVIKAR

IPC: H01L23/26 ,  H01L23/433

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.