公开(公告)号：US10998282B2

公开(公告)日：2021-05-04

申请号：US16561974

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： David Unruh ,  Srinivas V. Pietambaram

IPC: H01L23/00

Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US10438914B2

公开(公告)日：2019-10-08

申请号：US16039595

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： David Unruh ,  Srinivas V. Pietambaram

IPC: H01L23/00

Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US20190393178A1

公开(公告)日：2019-12-26

申请号：US16561974

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： David Unruh ,  Srinivas V. Pietambaram

IPC: H01L23/00

Abstract: An electroless nickel, electroless palladium, electroless tin stack and. associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US20200066626A1

公开(公告)日：2020-02-27

申请号：US16107655

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Jason M. Gamba ,  David Unruh ,  Adrian Kemal Bayraktaroglu ,  Thomas S. Heaton

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/48

Abstract: Disclosed herein are pocket structures, materials, and methods for integrated circuit (IC) package supports. For example, in some embodiments, an IC package support may include: an interconnect pocket having sidewalls provided by a dielectric material; and a conductive contact at a bottom of the interconnect pocket, wherein the conductive contact includes a first metal material and a second metal material, the first metal material provides a bottom surface of the interconnect pocket and is in contact with the dielectric material, the second metal material has a different composition than the first metal material, and the second metal material is in contact with the dielectric material.

公开(公告)号：US20180323162A1

公开(公告)日：2018-11-08

申请号：US16039595

申请日：2018-07-19

Applicant: Intel Corporation

Inventor： David Unruh ,  Srinivas V. Pietambaram

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/11464 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403

Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US10049996B2

公开(公告)日：2018-08-14

申请号：US15088711

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： David Unruh ,  Srinivas V. Pietambaram

IPC: H01L23/00

Abstract: An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include forming a layer of a second material over a first material at a base of a trench in a solder resist layer. The first material includes nickel and the second material includes palladium. The method further includes depositing a third material that includes tin on the second material using an electroless deposition process, and forming a solder bump out of the third material using a reflow and deflux process.

公开(公告)号：US11276634B2

公开(公告)日：2022-03-15

申请号：US16607601

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

公开(公告)号：US20200075473A1

公开(公告)日：2020-03-05

申请号：US16607601

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

公开(公告)号：US20190287915A1

公开(公告)日：2019-09-19

申请号：US16464995

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： David Unruh ,  Srinivas V. Pietambaram

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Methods/structures of forming package structures are described. Those methods/structures may include forming a first conductive trace adjacent a second conductive trace on a dielectric material of a high density package substrate. A barrier layer is formed on at least one of the first conductive trace or the second conductive trace, wherein the barrier layer comprises a corrosion resistant material, and forming a conductive via on a portion of the barrier layer.