公开(公告)号：US20180096764A1

公开(公告)日：2018-04-05

申请号：US15283350

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Donald S. GARDNER ,  Gerhard SCHROM ,  Edward A. BURTON

IPC: H01F1/147 ,  H01F27/255 ,  H01F10/06 ,  H01F27/28 ,  H01F41/04 ,  H01F41/16 ,  H01F41/26 ,  H01F41/32 ,  H05K3/00 ,  H01L23/64 ,  H01L49/02 ,  H01L25/18

CPC classification number: H01F1/14733 ,  H01F10/06 ,  H01F17/0006 ,  H01F27/255 ,  H01F27/2804 ,  H01F27/365 ,  H01F41/041 ,  H01F41/046 ,  H01F41/16 ,  H01F41/18 ,  H01F41/26 ,  H01F41/32 ,  H01F2017/0066 ,  H01L23/552 ,  H01L23/645 ,  H01L25/18 ,  H01L28/10 ,  H05K1/165 ,  H05K3/0085 ,  H05K2201/086 ,  H05K2201/09236

Abstract: Embodiments are generally directed to hybrid magnetic material structures for electronic devices and circuits. An embodiment of an inductor includes a first layer of magnetic film material applied on a substrate, one or more conductors placed on the first layer of magnetic film material, and a second layer of magnetic particles, wherein the magnetic particles are suspended in an insulating medium.

公开(公告)号：US20190206836A1

公开(公告)日：2019-07-04

申请号：US15859404

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Edward A. BURTON

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/3738 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: Stacked semiconductor die architectures having thermal spreaders disposed between stacked semiconductor dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) a base die; (ii) a plurality of stacked semiconductor dies arranged on the base die; and (iii) at least one thermal spreader disposed in one or more gaps between the plurality of stacked semiconductor dies or in one or more areas on the base die that are adjacent to the plurality of stacked semiconductor dies. The thermal spreaders can assist with thermal management of the dies, which can assist with improving the power density of the stacked semiconductor die architecture. At least one other stacked semiconductor die architecture s also described.

公开(公告)号：US20190006334A1

公开(公告)日：2019-01-03

申请号：US16060658

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Donald S. GARDNER ,  Edward A. BURTON ,  Gerhard SCHROM ,  Larry E. MOSLEY

IPC: H01L25/16 ,  H01L49/02 ,  H01L29/20 ,  H01L23/498 ,  H01L21/50 ,  H01L23/00

Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.