公开(公告)号：US12237620B2

公开(公告)日：2025-02-25

申请号：US17214397

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis

IPC: H01R13/6471 ,  H01R12/73 ,  H01R12/57 ,  H01R13/03

Abstract: Examples described herein relate to a pin arrangement that includes a first signal pin; a second signal pin; and multiple parallel ground pins positioned between the first and second signal pins. In some examples, the multiple parallel ground pins are coupled to a single pin connector coupled to a first device and a single pin connector coupled to a second device. In some examples, a first leg of the multiple parallel ground pins is positioned parallel to a portion of the first signal pin and wherein a second leg of the multiple parallel ground pins is positioned parallel to a portion of the second signal pin. In some examples, the multiple parallel ground pins provide a 1:N signal to ground ratio for signals transmitted through at least a portion of the first and second signal pins, where N is greater than 1.

公开(公告)号：US11587597B2

公开(公告)日：2023-02-21

申请号：US16911168

申请日：2020-06-24

Applicant: Intel Corporation

Inventor： Xiang Li ,  Phil Geng ,  George Vergis ,  Mani Prakash

IPC: G11C5/04 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40 ,  G06F1/18

Abstract: A connector includes mounting tabs that are extended relative to traditional mounting tabs. On a back side of the printed circuit board (PCB), the mounting tabs connect to a back plate. The mounting tabs extend through the PCB and connect with the back plate, which provides improved structural integrity. Depending on the connector, the use of the mounting tabs can use existing mounting holes for the connector and remove the need for additional mounting holes.

公开(公告)号：US20220353991A1

公开(公告)日：2022-11-03

申请号：US17866775

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Xiang Li ,  Konika Ganguly ,  George Vergis ,  Stephen Christianson ,  Xiaopeng Dong

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/14

Abstract: An example of an apparatus may comprise a first set of compression contact pads formed on a first side of a circuit board, a second set of compression contact pads formed on a second side of the circuit board opposite to the first side of the circuit board, where the first set of compression contact pads are respectively electrically connected to the second set of compression pads. An example of the circuit board may include a memory board. An example stackable memory module may include memory devices mounted to both sides of the memory board. Other examples are disclosed and claimed.

公开(公告)号：US20220217846A1

公开(公告)日：2022-07-07

申请号：US17700972

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Xiang Li ,  Konika Ganguly ,  George Vergis ,  Stephen Christianson ,  Xiaopeng Dong ,  Landon Hanks

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/18

Abstract: An embodiment of an electronic apparatus comprises a circuit board, one or more memory devices affixed to a top side of the circuit board, and one or more board-to-board connectors affixed to a bottom side of the circuit board to provide an external connection to signals of the one or more memory devices, where the one or more board-to-board connectors are located inward from outermost edges of the circuit board and where a first footprint defined by an outermost boundary of the one or more board-to-board connectors is substantially a same size as or smaller than a second footprint defined by an outermost boundary of the one or more memory devices. Other embodiments are disclosed and claimed.

公开(公告)号：US11250902B2

公开(公告)日：2022-02-15

申请号：US16584724

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Douglas Heymann ,  Wei P. Chen ,  Suresh Chittor ,  George Vergis

IPC: G11C11/40 ,  G06F13/16 ,  G11C11/406 ,  G01K13/00

Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

公开(公告)号：US10888010B2

公开(公告)日：2021-01-05

申请号：US16422854

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Phil Geng ,  George Vergis ,  Xiang Li

IPC: H05K7/12 ,  H05K1/11 ,  H05K7/10 ,  H05K7/14 ,  H01R12/73

Abstract: Embodiments are directed towards apparatuses, methods, and systems for a memory module, e.g., a dual in-line memory module (DIMM) including a first lengthwise edge along the DIMM and a second lengthwise edge, opposite the first lengthwise edge, to couple the DIMM with a printed circuit board (PCB). In embodiments, the DIMM includes one or more notches along the first lengthwise edge, to removeably couple with one or more flexible supports located at least partially along a length or width of a chassis and to engage the notches to assist in retention of the DIMM in the chassis to reduce a shock and/or vibration associated with a load of a plurality of DIMMs on the PCB. In some embodiments, the one or more flexible supports are coupled to a support structure, such as a pole mounted or otherwise coupled to a panel of the chassis. Additional embodiments may be described and claimed.

公开(公告)号：US10802532B2

公开(公告)日：2020-10-13

申请号：US16429872

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  Bill Nale

IPC: G06F1/06 ,  G06F13/42 ,  G11C7/10 ,  G11C5/04 ,  H01L23/00 ,  G11C5/06 ,  G06F3/06 ,  G06F12/00

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US10592445B2

公开(公告)日：2020-03-17

申请号：US16208224

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox ,  Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F11/16 ,  G06F13/16 ,  G11C11/4096 ,  G06F13/40 ,  G11C14/00 ,  G11C5/04 ,  G11C7/10

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US20190188165A1

公开(公告)日：2019-06-20

申请号：US16283498

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Girish C. Venkatraman ,  Rajesh Bhaskar ,  George Vergis ,  John R. Goles

IPC: G06F13/16 ,  G06F13/362 ,  G06F12/06

CPC classification number: G06F13/1694 ,  G06F12/0653 ,  G06F12/0692 ,  G06F13/1657 ,  G06F13/362

Abstract: In embodiments, a device includes an input interface to receive a broadcast command from a host computer, the broadcast command including an access mode indication, and decoding circuitry coupled with the interface. The decoding circuitry is to determine, based at least in part on the received access mode indication, that the broadcast command is directed to access one or more pre-defined setup or control registers of one or more devices, or to access one or more internal registers of the one or more devices, and, in response to the determination, implement the access to the setup or control registers, or to the one or more internal registers. In embodiments, the device is disposed on a memory module coupled to the host computer.

公开(公告)号：US10121528B2

公开(公告)日：2018-11-06

申请号：US14440068

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： George Vergis ,  Kuljit S. Bains ,  James A. McCall ,  Ge Chang

IPC: G06F12/00 ,  G11C11/4074 ,  G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G06F13/16 ,  G11C11/408

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.