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公开(公告)号:US10700051B2
公开(公告)日:2020-06-30
申请号:US15996870
申请日:2018-06-04
Applicant: Intel Corporation
Inventor: Robert L. Sankman , Sairam Agraharam , Shengquan Ou , Thomas J De Bonis , Todd Spencer , Yang Sun , Guotao Wang
IPC: H01L25/00 , H01L23/538 , H01L25/18 , H01L23/00 , H01L21/56
Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号:US12199085B2
公开(公告)日:2025-01-14
申请号:US17716934
申请日:2022-04-08
Applicant: Intel Corporation
Inventor: Robert L. Sankman , Sairam Agraharam , Shengquan Ou , Thomas J De Bonis , Todd Spencer , Yang Sun , Guotao Wang
IPC: H01L25/00 , H01L21/56 , H01L23/00 , H01L23/538 , H01L25/18
Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号:US11114388B2
公开(公告)日:2021-09-07
申请号:US16280993
申请日:2019-02-20
Applicant: INTEL CORPORATION
Inventor: Eric J. Li , Guotao Wang , Huiyang Fei , Sairam Agraharam , Omkar G. Karhade , Nitin A. Deshpande
Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
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公开(公告)号:US20190371778A1
公开(公告)日:2019-12-05
申请号:US15996870
申请日:2018-06-04
Applicant: Intel Corporation
Inventor: Robert L. Sankman , Sairam Agraharam , Shengquan Ou , Thomas J. De Bonis , Todd Spencer , Yang Sun , Guotao Wang
IPC: H01L25/00 , H01L21/56 , H01L23/538 , H01L25/18 , H01L23/00
Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号:US11817444B2
公开(公告)日:2023-11-14
申请号:US17587657
申请日:2022-01-28
Applicant: Intel Corporation
Inventor: Robert L Sankman , Sairam Agraharam , Shengquan Ou , Thomas J De Bonis , Todd Spencer , Yang Sun , Guotao Wang
IPC: H01L25/00 , H01L23/538 , H01L25/18 , H01L23/00 , H01L21/56
CPC classification number: H01L25/50 , H01L21/563 , H01L23/5381 , H01L23/5385 , H01L24/06 , H01L24/11 , H01L24/16 , H01L24/17 , H01L25/18 , H01L2224/0603 , H01L2224/11013 , H01L2224/16145 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/17051
Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号:US11348911B2
公开(公告)日:2022-05-31
申请号:US16892698
申请日:2020-06-04
Applicant: Intel Corporation
Inventor: Robert L. Sankman , Sairam Agraharam , Shengquan Ou , Thomas J De Bonis , Todd Spencer , Yang Sun , Guotao Wang
IPC: H01L23/538 , H01L25/00 , H01L25/18 , H01L23/00 , H01L21/56
Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号:US10256198B2
公开(公告)日:2019-04-09
申请号:US15468067
申请日:2017-03-23
Applicant: INTEL CORPORATION
Inventor: Eric J. Li , Guotao Wang , Huiyang Fei , Sairam Agraharam , Omkar G. Karhade , Nitin A. Deshpande
IPC: H01L23/12 , H01L23/053 , H01L23/00 , H01L23/498 , H01L23/31 , H05K3/30 , H05K3/34 , H01L21/48 , H05K1/18
Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
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