公开(公告)号：US11114388B2

公开(公告)日：2021-09-07

申请号：US16280993

申请日：2019-02-20

申请人： INTEL CORPORATION

发明人： Eric J. Li ,  Guotao Wang ,  Huiyang Fei ,  Sairam Agraharam ,  Omkar G. Karhade ,  Nitin A. Deshpande

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48

摘要： Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US10256198B2

公开(公告)日：2019-04-09

申请号：US15468067

申请日：2017-03-23

申请人： INTEL CORPORATION

发明人： Eric J. Li ,  Guotao Wang ,  Huiyang Fei ,  Sairam Agraharam ,  Omkar G. Karhade ,  Nitin A. Deshpande

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48 ,  H05K1/18

摘要： Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

公开(公告)号：US10231338B2

公开(公告)日：2019-03-12

申请号：US14748496

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： Naga Sivakumar Yagnamurthy ,  Huiyang Fei ,  Pramod Malatkar ,  Prasanna Raghavan ,  Robert Nickerson

IPC分类号： H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H05K1/11 ,  B29C70/84 ,  B29C70/70 ,  B29C70/88 ,  B29C37/00 ,  B29C33/00 ,  B29C69/00 ,  G11C11/401 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  B29K63/00 ,  B29L31/34 ,  G11C5/04 ,  H05K1/14

摘要： Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.

公开(公告)号：US09633937B2

公开(公告)日：2017-04-25

申请号：US14778128

申请日：2014-12-16

申请人： Intel Corporation

发明人： Huiyang Fei ,  Prasanna Raghavan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/13 ,  H01L23/16 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/13 ,  H01L23/16 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49883 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/384 ,  H01L2924/014 ,  H01L2924/00014

摘要： The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.

公开(公告)号：US20160381800A1

公开(公告)日：2016-12-29

申请号：US14748496

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： Naga Sivakumar Yagnamurthy ,  Huiyang Fei ,  Pramod Malatkar ,  Prasanna Raghavan ,  Robert Nickerson

IPC分类号： H05K1/18 ,  B29C70/84 ,  B29C70/70 ,  G11C11/401 ,  B29C37/00 ,  B29C33/00 ,  B29C69/00 ,  H05K1/11 ,  B29C70/88

CPC分类号： H05K1/181 ,  B29C33/0033 ,  B29C37/0025 ,  B29C69/001 ,  B29C70/70 ,  B29C70/84 ,  B29C70/882 ,  B29K2063/00 ,  B29K2995/0005 ,  B29L2031/3481 ,  G11C5/04 ,  G11C11/401 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/1815 ,  H05K1/111 ,  H05K1/144 ,  H05K2201/0379 ,  H05K2201/09036 ,  H05K2201/10159 ,  H05K2203/041

摘要： Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.

摘要翻译： 描述形成包括沟槽的封装结构的方法。 实施例包括设置在第一基板上的第一管芯和设置在第一基板的周边区域上的至少一个互连结构。 在第一基板的一部分上和第一模具上设置模塑料，其中沟槽开口设置在位于至少一个互连结构和第一模之间的模塑料中。