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公开(公告)号：US20160284404A1
公开(公告)日：2016-09-29
申请号：US14672130
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/16 , G11C13/0004 , G11C13/0061 , G11C2013/0078 , G11C2013/008 , G11C2013/0092 , H01L45/06 , H01L45/1286 , H01L45/141
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。
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2.发明公开公开(公告)号：US20230267988A1
公开(公告)日：2023-08-24
申请号：US17679971
申请日：2022-02-24
Applicant: Intel Corporation
Inventor： Lu Liu , Hemant P. Rao , Phoebe P. Yeoh , Raymond Zeng
IPC: G11C11/408 , G11C11/4094 , G11C11/4096 , G11C11/4072 , G11C11/4076 , G11C11/4074
CPC classification number: G11C11/4085 , G11C11/4094 , G11C11/4096 , G11C11/4072 , G11C11/4076 , G11C11/4074
Abstract: A method, apparatus and system. The apparatus includes one or more processors to: determine that a memory operation including one of a write operation or a read operation is to be implemented on a memory cell of a memory array, the memory operation having a duration equal to a latency window and being based on a voltage change across the memory cell equal to a target memory window; and in response to a determination that the memory operation is to be implemented, cause, during the latency window, an application to the memory cell of a current pulse amplitude profile progressively decreasing between and including at least four current pulse amplitudes.
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公开(公告)号：US10248351B1
公开(公告)日：2019-04-02
申请号：US15721388
申请日：2017-09-29
Applicant: INTEL CORPORATION
Inventor： Koushik Banerjee , Lu Liu , Sanjay Rangan , Enrico Varesi , Innocenzo Tortorelli , Hongmei Wang , Mattia Boniardi
Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
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4.发明申请公开(公告)号：US20190043576A1
公开(公告)日：2019-02-07
申请号：US15942329
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Koushik Banerjee , Lu Liu , Sanjay Rangan
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0035 , G11C13/004 , G11C2013/005 , G11C2013/0078 , G11C2013/0092 , G11C2213/15 , G11C2213/71
Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
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公开(公告)号：US09892785B2
公开(公告)日：2018-02-13
申请号：US15442594
申请日：2017-02-24
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/16 , G11C13/0004 , G11C13/0061 , G11C2013/0078 , G11C2013/008 , G11C2013/0092 , H01L45/06 , H01L45/1286 , H01L45/141
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
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Patent Agency Ranking
公开(公告)号：US09583187B2
公开(公告)日：2017-02-28
申请号：US14672130
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/16 , G11C13/0004 , G11C13/0061 , G11C2013/0078 , G11C2013/008 , G11C2013/0092 , H01L45/06 , H01L45/1286 , H01L45/141
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。
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公开(公告)号：US10884640B2
公开(公告)日：2021-01-05
申请号：US16373282
申请日：2019-04-02
Applicant: Intel Corporation
Inventor： Koushik Banerjee , Lu Liu , Sanjay Rangan , Enrico Varesi , Innocenzo Tortorelli , Hongmei Wang , Mattia Boniardi
Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
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公开(公告)号：US10796761B2
公开(公告)日：2020-10-06
申请号：US16520213
申请日：2019-07-23
Applicant: Intel Corporation
Inventor： Koushik Banerjee , Lu Liu , Sanjay Rangan
Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.
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公开(公告)号：US10446229B2
公开(公告)日：2019-10-15
申请号：US15894822
申请日：2018-02-12
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
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公开(公告)号：US20190102099A1
公开(公告)日：2019-04-04
申请号：US15721388
申请日：2017-09-29
Applicant: INTEL CORPORATION
Inventor： Koushik Banerjee , Lu Liu , Sanjay Rangan , Enrico Varesi , Innocenzo Tortorelli , Hongmei Wang , Mattia Boniardi
Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
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