公开(公告)号：US20250120143A1

公开(公告)日：2025-04-10

申请号：US18482192

申请日：2023-10-06

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Adam Brand ,  Chen-Guan Lee ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Adithya Shankar ,  Marko Radosavljevic

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in devices that include CFETs, either by implementing the extended drain transistor across both CFET layers, or by providing a sub-fin pedestal with the well regions in the lower layer.

公开(公告)号：US11100984B2

公开(公告)日：2021-08-24

申请号：US16748104

申请日：2020-01-21

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Sanjay Rangan

IPC: G11C8/00 ,  G11C13/00 ,  G11C11/56

Abstract: An apparatus is described. The apparatus includes a cross-point non volatile memory cell array comprised of a first plurality of access lines and a second orthogonal plurality of access lines. Each of the first plurality of access lines are coupled to a first address decoder through a respective pass transistor. The pass transistor is coupled to control circuitry to bias the pass transistor into one of at least two states that include a first active state determined from a second address decoder and a second active state determined from the second address decoder.

公开(公告)号：US09299747B1

公开(公告)日：2016-03-29

申请号：US14552205

申请日：2014-11-24

Applicant: Intel Corporation

Inventor： Fabio Pellizzer ,  Giulio Albini ,  Stephen W. Russell ,  Max F. Hineman ,  Sanjay Rangan

IPC: H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了增加相变存储器元件的电热隔离和相关技术的电极配置。 在一个实施例中，一种装置包括多个相变存储器（PCM）元件，其中多个PCM元件中的各个PCM元件包括相变材料层，设置在相变材料层上的第一电极层和 与所述相变材料层直接接触，以及设置在所述第一电极层上并与所述第一电极层直接接触的第二电极层。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10248351B1

公开(公告)日：2019-04-02

申请号：US15721388

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

公开(公告)号：US20190043576A1

公开(公告)日：2019-02-07

申请号：US15942329

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/004 ,  G11C2013/005 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/71

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

公开(公告)号：US09892785B2

公开(公告)日：2018-02-13

申请号：US15442594

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

IPC: G11C11/16 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/141

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

公开(公告)号：US09583187B2

公开(公告)日：2017-02-28

申请号：US14672130

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/141

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。

公开(公告)号：US11107523B1

公开(公告)日：2021-08-31

申请号：US16828589

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal

IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00

Abstract: Multi-level cell (MLC) cross-point memory cells can store more than 1 bit per cell. In one example, MLC write operations for cross-point memory can be achieved by independently changing the state of the switch element and the memory element. The memory cell can be programmed to multiple states, such as a high threshold voltage state (where both the memory element and switch element exhibit a high threshold voltage or resistance), a low threshold voltage state (where both the memory element and select element exhibit a low threshold voltage or resistance), and one or more intermediate resistance states. In one example, additional resistance states can be programmed by setting the switch element and memory element to opposite states (e.g., one of the switch element and memory element is in a high resistance state and the other is in a low resistance state) or by placing both the switch element and memory element in different intermediate states.

公开(公告)号：US09608042B2

公开(公告)日：2017-03-28

申请号：US15017552

申请日：2016-02-05

Applicant: INTEL CORPORATION

Inventor： Fabio Pellizzer ,  Giulio Albini ,  Stephen W. Russell ,  Max F. Hineman ,  Sanjay Rangan

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20160284404A1

公开(公告)日：2016-09-29

申请号：US14672130

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/141

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。