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    Non volatile cross point memory having word line pass transistor with multiple active states
    1.
    发明授权
    Non volatile cross point memory having word line pass transistor with multiple active states 有权

    公开(公告)号：US11100984B2

    公开(公告)日：2021-08-24

    申请号：US16748104

    申请日：2020-01-21

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Sanjay Rangan

    IPC: G11C8/00 ,  G11C13/00 ,  G11C11/56

    Abstract: An apparatus is described. The apparatus includes a cross-point non volatile memory cell array comprised of a first plurality of access lines and a second orthogonal plurality of access lines. Each of the first plurality of access lines are coupled to a first address decoder through a respective pass transistor. The pass transistor is coupled to control circuitry to bias the pass transistor into one of at least two states that include a first active state determined from a second address decoder and a second active state determined from the second address decoder.

    Tailoring timing offsets during a programming pulse for a memory device
    2.
    发明授权
    Tailoring timing offsets during a programming pulse for a memory device 有权

    公开(公告)号：US10553286B2

    公开(公告)日：2020-02-04

    申请号：US16147422

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Daniel Chu ,  Shravya Gottipati

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.

    Set technique for phase change memory
    4.
    发明授权
    Set technique for phase change memory 有权

    公开(公告)号：US10248351B1

    公开(公告)日：2019-04-02

    申请号：US15721388

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    SET TECHNIQUE FOR PHASE CHANGE MEMORY
    6.
    发明申请
    SET TECHNIQUE FOR PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20190324671A1

    公开(公告)日：2019-10-24

    申请号：US16373282

    申请日：2019-04-02

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    Tailoring current magnitude and duration during a programming pulse for a memory device
    7.
    发明授权
    Tailoring current magnitude and duration during a programming pulse for a memory device 有权

    公开(公告)号：US10360977B2

    公开(公告)日：2019-07-23

    申请号：US15942329

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan

    IPC: G11C16/04 ,  G11C13/00

    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

    Set technique for phase change memory
    8.
    发明授权
    Set technique for phase change memory 有权

    公开(公告)号：US10884640B2

    公开(公告)日：2021-01-05

    申请号：US16373282

    申请日：2019-04-02

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    Tailoring current magnitude and duration during a programming pulse for a memory device
    9.
    发明授权
    Tailoring current magnitude and duration during a programming pulse for a memory device 有权

    公开(公告)号：US10796761B2

    公开(公告)日：2020-10-06

    申请号：US16520213

    申请日：2019-07-23

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan

    IPC: G11C16/04 ,  G11C13/00

    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

    SET TECHNIQUE FOR PHASE CHANGE MEMORY
    10.
    发明申请
    SET TECHNIQUE FOR PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20190102099A1

    公开(公告)日：2019-04-04

    申请号：US15721388

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F3/06 ,  G11C13/00

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

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