中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.025 seconds)

    Reset refresh techniques for self-selecting memory
    2.
    发明授权
    Reset refresh techniques for self-selecting memory 有权

    公开(公告)号：US10777275B2

    公开(公告)日：2020-09-15

    申请号：US16143033

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Agostino Pirovano ,  Hernan A. Castro ,  Innocenzo Tortorelli ,  Andrea Redaelli

    IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.

    SET TECHNIQUE FOR PHASE CHANGE MEMORY
    3.
    发明申请
    SET TECHNIQUE FOR PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20190324671A1

    公开(公告)日：2019-10-24

    申请号：US16373282

    申请日：2019-04-02

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    Set technique for phase change memory
    5.
    发明授权
    Set technique for phase change memory 有权

    公开(公告)号：US10248351B1

    公开(公告)日：2019-04-02

    申请号：US15721388

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    Multi-deck memory device with inverted deck
    7.
    发明授权
    Multi-deck memory device with inverted deck 有权

    公开(公告)号：US10163982B2

    公开(公告)日：2018-12-25

    申请号：US15474154

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Andrea Redaelli ,  Innocenzo Tortorelli ,  Fabio Pellizzer ,  Agostino Pirovano ,  DerChang Kau

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  G11C13/00

    Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.

    Double-polarity memory read
    8.
    发明授权
    Double-polarity memory read 有权

    公开(公告)号：US10102891B2

    公开(公告)日：2018-10-16

    申请号：US15786317

    申请日：2017-10-17

    Applicant: Intel Corporation

    Inventor： Innocenzo Tortorelli ,  Federico Pio

    IPC: G11C7/22 ,  G11C7/06 ,  G11C13/00

    Abstract: Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more of the plurality of memory cells. The method involves detecting electrical responses of the one or more memory cells to the first voltage and the second voltage. The method also involves determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

    Set technique for phase change memory
    9.
    发明授权
    Set technique for phase change memory 有权

    公开(公告)号：US10884640B2

    公开(公告)日：2021-01-05

    申请号：US16373282

    申请日：2019-04-02

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    SET TECHNIQUE FOR PHASE CHANGE MEMORY
    10.
    发明申请
    SET TECHNIQUE FOR PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20190102099A1

    公开(公告)日：2019-04-04

    申请号：US15721388

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F3/06 ,  G11C13/00

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

Patent Agency Ranking