公开(公告)号：US20240204048A1

公开(公告)日：2024-06-20

申请号：US18082851

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Hwichan Jun

IPC: H01L29/08 ,  H01L23/00 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/0843 ,  H01L24/10 ,  H01L27/085 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L2224/13023

Abstract: Techniques are provided herein to form semiconductor devices having one or more epitaxial source or drain regions wrapped by a conductive contact to form an improved ohmic contact. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between the first source or drain region and a third source or drain region. The first and second semiconductor devices include a subfin region adjacent to a dielectric layer. A conductive layer extends around the first source or drain region such that the conductive layer at least contacts the sidewalls of the first source or drain region and both upper and lower surfaces of the source or drain region. A dielectric layer is also present between the conductive contact and the subfin region.

公开(公告)号：US20240194673A1

公开(公告)日：2024-06-13

申请号：US18077394

申请日：2022-12-08

Applicant: Intel Corporation

Inventor： Hwichan Jun ,  Guillaume Bouche

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/785

Abstract: Techniques to form semiconductor devices that include both finFET and gate-all-around (GAA) devices on same substrate. The finFET and GAA devices may have different gate oxide thicknesses and/or shallow trench isolation (STI) thicknesses, along with coplanar channel regions. In an example, a first semiconductor device includes a finFET structure with a first gate structure around or otherwise on a semiconductor fin while a second semiconductor device includes a GAA structure with a second gate structure around or otherwise on a plurality of semiconductor bodies (e.g., nanoribbons). The first gate structure includes a first gate dielectric and a first gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) and the second gate structure includes a second gate dielectric and a second gate electrode. The first gate dielectric includes a first gate oxide layer that is thicker than a second gate oxide layer of the second gate dielectric.

公开(公告)号：US20240186327A1

公开(公告)日：2024-06-06

申请号：US18074814

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Hwichan Jun ,  Guillaume Bouche

IPC: H01L27/12 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/1237 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/127

Abstract: Techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. A first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. The first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. The first gate oxide layer is thicker than the second gate oxide layer. A high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer.

公开(公告)号：US20240421002A1

公开(公告)日：2024-12-19

申请号：US18333758

申请日：2023-06-13

Applicant: Intel Corporation

Inventor： Hwichan Jun ,  Edward Yeh ,  Robin Chao

IPC: H01L21/8234 ,  H01L27/088

Abstract: An IC device includes a gate electrode having multiple lengths. The length of a first portion of the gate electrode, which is over a channel region in a semiconductor structure, may be longer (e.g., about 0.5-3 nm longer) than the length of a second portion of the gate electrode, which is over a channel region in another semiconductor structure. The pitches at the two portions of the gate electrode may be the same or substantially similar. The lengths of the gate electrode can be differentiated by using dry clean based removal of a dielectric material surrounding the semiconductor structures. A larger amount of the dielectric material may be removed at a first region than a second region so that the gap at the first region can be longer than the gap at the second region. A conductive material may be provided to fill the gaps to form the gate electrode.

公开(公告)号：US20240213324A1

公开(公告)日：2024-06-27

申请号：US18087318

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Tuhin Guha Neogi ,  Hwichan Jun ,  Francis Goodwin

IPC: H01L29/10 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L29/1041 ,  H01L25/0655 ,  H01L29/0669 ,  H01L29/1095

Abstract: Techniques are provided herein to form semiconductor devices that include an elongated contact having two different heights on a source or drain region. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a source or drain region. An elongated conductive contact is formed over the source or drain region that stretches or otherwise extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. A conductive via may contact the portion of the conductive contact over the adjacent source or drain region. Accordingly, the conductive contact may have a first thickness above the source or drain region and a second thickness above the adjacent source or drain region with the first thickness being greater than the second thickness.