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    Signal detection techniques using clock data recovery
    3.
    发明授权
    Signal detection techniques using clock data recovery 有权

    公开(公告)号：US10797855B2

    公开(公告)日：2020-10-06

    申请号：US16036227

    申请日：2018-07-16

    Applicant: INTEL CORPORATION

    Inventor： Amir Laufer ,  Itamar Levin ,  Kevan A. Lillie

    IPC: H04L7/04 ,  H03L7/08 ,  H03L7/091 ,  H04L7/00 ,  H04L7/033

    Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

    Ethernet auto-negotiation with parallel detect for 10G DAC or other non-auto-negotiated modes
    4.
    发明授权
    Ethernet auto-negotiation with parallel detect for 10G DAC or other non-auto-negotiated modes 有权

    公开(公告)号：US10164912B2

    公开(公告)日：2018-12-25

    申请号：US15218681

    申请日：2016-07-25

    Applicant: Intel Corporation

    Inventor： Adee O. Ran ,  David L. Chalupsky ,  Kevan A. Lillie ,  Richard I. Mellitz ,  Kent C. Lusted

    IPC: H04L12/935

    Abstract: Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.

    Signal detection techniques using clock data recovery
    7.
    发明授权
    Signal detection techniques using clock data recovery 有权

    公开(公告)号：US10027470B1

    公开(公告)日：2018-07-17

    申请号：US15393186

    申请日：2016-12-28

    Applicant: INTEL CORPORATION

    Inventor： Amir Laufer ,  Itamar Levin ,  Kevan A. Lillie

    IPC: H04L7/04 ,  H04L7/00 ,  H03L7/08

    Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

    Techniques for testing receiver operation
    9.
    发明授权
    Techniques for testing receiver operation 有权
    测试接收机操作的技术

    公开(公告)号：US09473259B2

    公开(公告)日：2016-10-18

    申请号：US14550822

    申请日：2014-11-21

    Applicant: INTEL CORPORATION

    Inventor： Itamar Levin ,  Kevan A. Lillie ,  Dima Hammed ,  Elior Segev ,  Mingming Xu ,  Tomer Fael

    IPC: H04B17/00 ,  H04B17/24 ,  H04B17/29 ,  H04L25/03

    CPC classification number: H04B17/24 ,  G06F11/221 ,  H04B17/00 ,  H04B17/29 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03878

    Abstract: Various embodiments are generally directed to techniques for testing a receiver incorporated into an IC to receive a bitstream. An apparatus includes a precharge component to set a VGA to output a differential bias voltage; a taps component to set a tap to form a feedback loop that extends from an output of the bit slicer to the input of the bit slicer through a delay circuit and the tap, the tap to output a first differential voltage to the input of the bit slicer to invert a polarity of a sum of differential voltages at the input of the bit slicer to enable oscillation of the bit slicer, the sum generated from at least the differential bias voltage and the first differential voltage; and a capture component coupled to the output of the bit slicer to capture a series of bit values therefrom. Other embodiments are described and claimed.

    Abstract translation: 各种实施例通常涉及用于测试结合到IC中以接收比特流的接收机的技术。 一种装置包括：预充电部件，用于设置VGA以输出差分偏置电压; 抽头分量，用于设置抽头以形成反馈环路，该反馈环路通过延迟电路和抽头从位限幅器的输出延伸到位限幅器的输入，该抽头将第一差分电压输出到位的输入端 切片器，以在位限幅器的输入处反转差分电压之和的极性，以使得位限幅器的振荡，至少从差分偏置电压和第一差分电压产生的和; 以及耦合到所述位限幅器的输出以从其捕获一系列位值的捕获元件。 描述和要求保护其他实施例。

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