公开(公告)号：US11476190B2

公开(公告)日：2022-10-18

申请号：US16464565

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Balijeet S. Bains ,  Charles H. Wallace ,  Zhanping Chen

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.

公开(公告)号：US11239149B2

公开(公告)日：2022-02-01

申请号：US15942952

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Vincent Dorgan ,  Jeffrey Hicks ,  Uddalak Bhattacharya ,  Zhanping Chen ,  Walid Hafez

IPC: G11C11/00 ,  H01L23/50 ,  H01L21/768 ,  H01L21/77

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

公开(公告)号：US20230162772A1

公开(公告)日：2023-05-25

申请号：US17706124

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Yu-Lin Chao ,  Zhanping Chen ,  Sarvesh Kulkarni ,  Rachael Parker ,  Jyothi Bhaskarr Velamala

IPC: G11C7/24 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C7/24 ,  G11C17/16 ,  G11C17/18

Abstract: Hot carrier injection (HCI) may be used to provide various improvements for one-time programmable (OTP) read-only memory (ROM) or physical unclonable function (PUF) circuits. HCI may be used to write a memory bit (e.g., logical 0 or 1), which may be used in OTP ROM. HCI may be used to provide improved programmable ROM (PROM) memory devices, such as to facilitate programming or to increase sensing window. HCI may also be used to write a memory bit in a PUF circuit. HCI may provide a cross-foundry portable PUF circuit that has an associated adjustable bit error rate (BER), which may be used to secure root key generation, or may be used to provide a unique identification (ID) for fuse replacement.

公开(公告)号：US09679845B2

公开(公告)日：2017-06-13

申请号：US15124867

申请日：2014-05-08

Applicant: Intel Corporation

Inventor： Zhanping Chen ,  Andrew W. Yeoh ,  Seongtae Jeong ,  Uddalak Bhattacharya ,  Charles H. Wallace

IPC: H01L23/525 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.

公开(公告)号：US09123724B2

公开(公告)日：2015-09-01

申请号：US14134097

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Xianghong Tong ,  Zhanping Chen ,  Walid M. Hafez ,  Zhiyong Ma ,  Sarvesh H. Kulkarni ,  Kevin X. Zhang ,  Matthew B. Pedersen ,  Kevin D. Johnson

IPC: H01L27/11 ,  H01L29/04 ,  H01L21/02 ,  H01L23/58 ,  H01L23/525 ,  H01L27/02 ,  H01L27/112 ,  H01L27/06 ,  H01L21/44 ,  H01L29/861

CPC classification number: H01L23/5252 ,  H01L21/44 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Abstract translation: 描述了形成和使用微电子结构的方法。 实施例包括在金属熔丝栅极和PMOS器件之间形成二极管，其中二极管设置在金属熔丝栅极的触点和PMOS器件的触点之间，并且其中二极管将金属熔丝栅极的触点耦合到 PMOS器件的接触。