公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20200006180A1

公开(公告)日：2020-01-02

申请号：US16024697

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Andrew BROWN ,  Ji Yong PARK ,  Siddharth ALUR ,  Cheng XU ,  Amruthavalli ALUR

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/29

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

公开(公告)号：US20190393143A1

公开(公告)日：2019-12-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20190287934A1

公开(公告)日：2019-09-19

申请号：US15921511

申请日：2018-03-14

Applicant: Intel Corporation

Inventor： Yikang DENG ,  Jonathan ROSCH ,  Andrew BROWN ,  Junnan ZHAO

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01F27/40

Abstract: Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.