公开(公告)号：US20190295937A1

公开(公告)日：2019-09-26

申请号：US15927047

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Ying WANG ,  Cheng XU ,  Hongxia FENG ,  Meizi JIAO ,  Junnan ZHAO ,  Yikang DENG

IPC: H01L23/498 ,  C23C18/26 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points.

公开(公告)号：US20190027431A1

公开(公告)日：2019-01-24

申请号：US15654399

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20230238368A1

公开(公告)日：2023-07-27

申请号：US18128952

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L23/5386 ,  H01L28/40 ,  H01L23/49811 ,  H01L21/568 ,  H01L23/528 ,  H01L2224/16265 ,  H01L2224/1623

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20190272936A1

公开(公告)日：2019-09-05

申请号：US15911549

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Ying WANG ,  Junnan ZHAO ,  Meizi JIAO ,  Yikang DENG

IPC: H01F27/24 ,  G05F1/10 ,  H01L49/02 ,  H01F41/02

Abstract: Embodiments include inductors with embedded magnetic cores and methods of forming such inductors. Some embodiments may include an integrated circuit package that utilizes such inductors. For example, the integrated circuit package may include an integrated circuit die and a multi-phase voltage regulator electrically coupled to the integrated circuit die. In an embodiment, the multi-phase voltage regulator includes a substrate core and a plurality of inductors in the substrate core. In an embodiment, the inductors may include a conductive loop in and around the substrate core. In an embodiment, the conductive loops are electrically coupled to a voltage out line. Embodiments may also include a magnetic core surrounded by the conductive loops. The magnetic core is separated from surfaces of the conductive loops by the substrate core

公开(公告)号：US20210327800A1

公开(公告)日：2021-10-21

申请号：US17364686

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20180315690A1

公开(公告)日：2018-11-01

申请号：US15773030

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F27/28 ,  H01L49/02 ,  H01F41/04 ,  H01L21/48 ,  H01G4/33 ,  H01L23/66

CPC classification number: H01F27/40 ,  H01F17/0006 ,  H01L28/00

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20240405006A1

公开(公告)日：2024-12-05

申请号：US18805232

申请日：2024-08-14

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.