公开(公告)号：US20170351641A1

公开(公告)日：2017-12-07

申请号：US15490743

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： ZEEV SPERBER ,  ROBERT VALENTINE ,  SHLOMO RAIKIN ,  STANISLAV SHWARTSMAN ,  GAL OFIR ,  IGOR YANOVER ,  GUY PATKIN ,  OFER LEVY

IPC: G06F15/78 ,  G06F9/345 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

公开(公告)号：US20170344483A1

公开(公告)日：2017-11-30

申请号：US15168980

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： STANISLAV SHWARTSMAN ,  RON RAIS

IPC: G06F12/0862 ,  G06F12/0875

Abstract: In an embodiment, a processor includes a plurality of cores, with at least one core including prefetch logic. The prefetch logic comprises circuitry to: receive a prefetch request; compare the received prefetch request to a plurality of entries of a prefetch filter cache; and in response to a determination that the received prefetch request matches one of the plurality of entries of the prefetch filter cache, drop the received prefetch request. Other embodiments are described and claimed.

公开(公告)号：US20160328172A1

公开(公告)日：2016-11-10

申请号：US14706936

申请日：2015-05-07

Applicant: INTEL CORPORATION

Inventor： LIHU RAPPOPORT ,  JARED W. STARK ,  KAMIL GARIFULLIN ,  FRANCK SALA ,  PAVEL I. KRYUKOV ,  STANISLAV SHWARTSMAN

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0631 ,  G06F3/06 ,  G06F3/0604 ,  G06F3/0671 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F12/0802

Abstract: A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

Abstract translation: 描述了使用虚拟寄存器进行有效的存储器重命名预测的方法和装置。 例如，设备的一个实施例包括：存储器执行单元（MEU），用于执行存储和加载操作，以分别将存储数据存储到存储器中并从存储器加载数据; 分配给存储和加载操作的多个存储器重命名（MRN）寄存器，每个MRN寄存器存储与存储操作相关联的数据，使得数据可用于后续加载操作; 以及至少一个MRN预测器，其包括用于向每个MRN寄存器分配虚拟存储器重命名（VMRN）寄存器的数据结构，MRN预测器，使用标识MRN的值来响应于负载和/或存储操作来查询数据结构 分配给负载和/或存储操作的寄存器，以确定与负载和/或存储操作相关联的当前VMRN寄存器。

公开(公告)号：US20150378633A1

公开(公告)日：2015-12-31

申请号：US14320334

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： RAVI L. SAHITA ,  VEDVYAS SHANBHOGUE ,  GILBERT NEIGER ,  JONATHAN EDWARDS ,  IDO OUZIEL ,  BARRY E. HUNTLEY ,  STANISLAV SHWARTSMAN ,  DAVID M. DURHAM ,  ANDREW V. ANDERSON ,  MICHAEL LEMAY

IPC: G06F3/06 ,  G06F9/455 ,  G06F12/10

CPC classification number: G06F9/45558 ,  G06F9/3004 ,  G06F9/30076 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/657

Abstract: An apparatus and method for fine grain memory protection. For example, one embodiment of a method comprises: performing a first lookup operation using a virtual address to identify a physical address of a memory page, the memory page comprising a plurality of sub-pages; determining whether sub-page permissions are enabled for the memory page; if sub-page permissions are enabled, then performing a second lookup operation to determine permissions associated with one or more of the sub-pages of the memory page; and implementing the permissions associated with the one or more sub-pages.

Abstract translation: 一种细粒度记忆保护装置和方法。 例如，方法的一个实施例包括：使用虚拟地址执行第一查找操作以识别存储器页面的物理地址，所述存储器页面包括多个子页面; 确定是否为所述存储器页启用子页面许可; 如果启用子页面许可，则执行第二查找操作以确定与存储器页面的一个或多个子页面相关联的许可; 以及实现与一个或多个子页面相关联的许可。