公开(公告)号：US20190006294A1

公开(公告)日：2019-01-03

申请号：US16002926

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kang Eu Ong ,  Bok Eng Chea ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/552

Abstract: Stiffener technology for electronic device packages is disclosed. A stiffener for a package substrate can include a top portion configured to be affixed to a top surface of a package substrate. The stiffener for a package substrate can also include a lateral portion extending from the top portion and configured to be disposed about a lateral side of the package substrate. An electronic device package and associated systems and methods are also disclosed.

公开(公告)号：US20180374833A1

公开(公告)日：2018-12-27

申请号：US15861421

申请日：2018-01-03

Applicant: Intel Corporation

Inventor： Shaw Fong Wong ,  Wei Keat P. Loh ,  Kang Eu Ong ,  AU Seong Wong

IPC: H01L25/10

Abstract: Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

公开(公告)号：US09397016B2

公开(公告)日：2016-07-19

申请号：US14500557

申请日：2014-09-29

Applicant: Intel Corporation

Inventor： Weng Khoon Mong ,  A. Vethanayagam Rudge ,  Bok Sim Lim ,  Mun Leong Loke ,  Kang Eu Ong ,  Sih Fei Lim ,  Tean Wee Ong

IPC: H01L23/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/50 ,  H01L23/31

CPC classification number: H01L23/12 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/562 ,  H01L24/16 ,  H01L24/17 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提出了用于电子基板的选择性无电镀。 在这方面，引入了一种方法，包括接收无芯衬底条，将焊球附着到无芯衬底条的背面，以及在焊球之间形成背面加强模。 还公开并要求保护其他实施例。

公开(公告)号：US20150076692A1

公开(公告)日：2015-03-19

申请号：US14500557

申请日：2014-09-29

Applicant: Intel Corporation

Inventor： Weng Khoon Mong ,  A. Vethanayagam Rudge ,  Bok Sim Lim ,  Mun Leong Loke ,  Kang Eu Ong ,  Sih Fei Lim ,  Tean Wee Ong

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/12 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/562 ,  H01L24/16 ,  H01L24/17 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.