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    CHARGE INJECTOR WITH INTEGRATED LEVEL SHIFTER FOR LOCALIZED MITIGATION OF SUPPLY VOLTAGE DROOP
    1.
    发明申请
    CHARGE INJECTOR WITH INTEGRATED LEVEL SHIFTER FOR LOCALIZED MITIGATION OF SUPPLY VOLTAGE DROOP 审中-公开

    公开(公告)号：US20190288681A1

    公开(公告)日：2019-09-19

    申请号：US15925396

    申请日：2018-03-19

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Minki Cho ,  Pascal Meinerzhagen ,  Muhammad Khellah

    IPC: H03K17/16 ,  H03K17/10 ,  H03K17/284

    Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

    Calibrated biasing of sleep transistor in integrated circuits
    7.
    发明授权
    Calibrated biasing of sleep transistor in integrated circuits 有权

    公开(公告)号：US10454476B2

    公开(公告)日：2019-10-22

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS
    9.
    发明申请
    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190044512A1

    公开(公告)日：2019-02-07

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  H03K19/0013

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

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