公开(公告)号：US09580776B2

公开(公告)日：2017-02-28

申请号：US14860341

申请日：2015-09-21

Applicant: INTEL CORPORATION

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/78 ,  H01L27/088 ,  C22C30/00 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

Abstract translation: 本说明书涉及制造具有非平面晶体管的微电子器件的领域。 本说明书的实施例涉及在非平面NMOS晶体管内形成栅极，其中可将NMOS功能材料（例如铝，钛和碳的组成）与含钛栅极填充物结合使用 以便于在形成非平面NMOS晶体管栅极的栅电极时使用含钨导电材料。

公开(公告)号：US20170117378A1

公开(公告)日：2017-04-27

申请号：US15401965

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L27/092 ,  H01L29/417 ,  H01L23/522 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/78 ,  C23C14/06

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US10020375B2

公开(公告)日：2018-07-10

申请号：US15726609

申请日：2017-10-06

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/49 ,  C23C14/06 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US20160035724A1

公开(公告)日：2016-02-04

申请号：US14860336

申请日：2015-09-21

Applicant: INTEL CORPORATION

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L27/088 ,  H01L29/51 ,  C22C30/00 ,  H01L29/06 ,  C22C14/00 ,  C22C21/00 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US20240006358A1

公开(公告)日：2024-01-04

申请号：US17854813

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Zhihua Zou ,  Omkar Karhade ,  Botao Zhang ,  Julia Chiu ,  Vivek Chidambaram ,  Yi Shi ,  Mohit Bhatia ,  Mostafa Aghazadeh

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.

公开(公告)号：US20180047825A1

公开(公告)日：2018-02-15

申请号：US15726609

申请日：2017-10-06

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L23/522 ,  C23C14/06 ,  H01L29/78

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US20240319437A1

公开(公告)日：2024-09-26

申请号：US18189844

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Julia Chiu ,  Chia-Pin Chiu ,  Kaveh Hosseini ,  Madhubanti Chatterjee

IPC: G02B6/12 ,  G02B6/136

CPC classification number: G02B6/12002 ,  G02B6/136

Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.

公开(公告)号：US09812546B2

公开(公告)日：2017-11-07

申请号：US15401965

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  C23C14/06 ,  H01L29/417 ,  H01L23/522 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

公开(公告)号：US09637810B2

公开(公告)日：2017-05-02

申请号：US14860336

申请日：2015-09-21

Applicant: INTEL CORPORATION

Inventor： Sameer S. Pradhan ,  Daniel B. Bergstrom ,  Jin-Sung Chun ,  Julia Chiu

IPC: H01L27/088 ,  C22C30/00 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/4966 ,  C22C30/00 ,  C23C14/0635 ,  C23C14/0652 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.