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公开(公告)号：US20170357448A1
公开(公告)日：2017-12-14
申请号：US15496588
申请日：2017-04-25
Applicant: Intel Corporation
Inventor： Brian Dees , Knut Grimsrud
CPC classification number: G06F3/061 , G06F3/0644 , G06F3/067 , G06F9/451
Abstract: Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and processes associated with each application executing on a system, apply one or more priority rules to the identified applications and processes to generate priority information, and transmit the priority information to a subsystem. The subsystem then matches received requests with the priority information and services the processes according to the priority information.
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公开(公告)号：US09645743B2
公开(公告)日：2017-05-09
申请号：US14500065
申请日：2014-09-29
Applicant: Intel Corporation
Inventor： Brian Dees , Knut Grimsrud
CPC classification number: G06F3/061 , G06F3/0644 , G06F3/067 , G06F9/451
Abstract: Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and processes associated with each application executing on a system, apply one or more priority rules to the identified applications and processes to generate priority information, and transmit the priority information to a subsystem. The subsystem then matches received requests with the priority information and services the processes according to the priority information.
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公开(公告)号：US20190087374A1
公开(公告)日：2019-03-21
申请号：US16191555
申请日：2018-11-15
Applicant: Intel Corporation
Inventor： Jawad Khan , Knut Grimsrud
Abstract: An embodiment of an extensible memory hub may include one or more upstream interface ports to couple the extensible memory hub to the controller, one or more downstream interface ports to couple the extensible memory hub to one or more of the nonvolatile memory and another extensible memory hub, and a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports and a second clock signal at a second frequency to the one or more downstream interface ports, where the first frequency may be different from the second frequency. Other embodiments are disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20170024275A1
公开(公告)日：2017-01-26
申请号：US15076377
申请日：2016-03-21
Applicant: Intel Corporation
Inventor： Knut Grimsrud , Jawad Khan , Richard Mangold
IPC: G06F11/10
CPC classification number: G06F11/1004 , G06F11/1016
Abstract: Apparatus, systems, and methods to manage high capacity memory devices are described. In one example, a controller comprises logic to receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA), compute a first system cyclic redundancy check (CRC) using a payload CRC, the namespace ID and the first extended LBA, store the first system CRC in association with the first extended LBA in a local memory, and write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a memory. Other examples are also disclosed and claimed.
Abstract translation: 描述了用于管理高容量存储器件的装置，系统和方法。 在一个示例中，控制器包括用于接收包括有效载荷数据，命名空间标识符（ID）和第一扩展逻辑块地址（LBA））的写操作的逻辑，使用有效载荷CRC计算第一系统循环冗余校验（CRC）， 命名空间ID和第一扩展LBA，在本地存储器中存储与第一扩展LBA相关联的第一系统CRC，并将有效载荷数据，第一系统CRC和从第一扩展LBA导出的截断的LBA写入存储器。 还公开并要求保护其他实例。
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公开(公告)号：US10990151B2
公开(公告)日：2021-04-27
申请号：US16292825
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Knut Grimsrud , Adrian Mocanu , Andrew Morning-Smith , Zeljko Zupanc
Abstract: In embodiments, an apparatus includes a burst current monitor, to detect a burst of input current drawn by a SSD from a host above a pre-defined burst threshold, and control logic coupled to the burst current monitor. The control logic, in response to the detection by the burst current monitor of the input current above the burst threshold, causes a capacitor of the SSD to supply an assistance current to the SSD, to reduce the input current drawn by the SSD. In embodiments, the capacitor is a hold-up capacitor disposed in a PLI circuit of the SSD, and the apparatus is integrated within a hold-up control logic sub-circuit of the PLI circuit.
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公开(公告)号：US20190196562A1
公开(公告)日：2019-06-27
申请号：US16292825
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Knut Grimsrud , Adrian Mocanu , Andrew Morning-Smith , Zeljko Zupanc
Abstract: In embodiments, an apparatus includes a burst current monitor, to detect a burst of input current drawn by a SSD from a host above a pre-defined burst threshold, and control logic coupled to the burst current monitor. The control logic, in response to the detection by the burst current monitor of the input current above the burst threshold, causes a capacitor of the SSD to supply an assistance current to the SSD, to reduce the input current drawn by the SSD. In embodiments, the capacitor is a hold-up capacitor disposed in a PLI circuit of the SSD, and the apparatus is integrated within a hold-up control logic sub-circuit of the PLI circuit.
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公开(公告)号：US10261701B2
公开(公告)日：2019-04-16
申请号：US15600592
申请日：2017-05-19
Applicant: INTEL CORPORATION
Inventor： Brian Dees , Knut Grimsrud , Rick Coulson
IPC: G06F3/06 , G06F1/14 , G06F12/0868 , G06F1/3287 , G06F9/4401 , G06F12/0866
Abstract: Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.
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公开(公告)号：US09292379B2
公开(公告)日：2016-03-22
申请号：US14040651
申请日：2013-09-28
Applicant: Intel Corporation
Inventor： Knut Grimsrud , Jawad Khan , Richard Mangold
CPC classification number: G06F11/1004 , G06F11/1016
Abstract: Apparatus, systems, and methods to manage high capacity memory devices are described. In one example, a controller comprises logic to receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA), compute a first system cyclic redundancy check (CRC) using a payload CRC, the namespace ID and the first extended LBA, store the first system CRC in association with the first extended LBA in a local memory, and write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a memory. Other examples are also disclosed and claimed.
Abstract translation: 描述了用于管理高容量存储器件的装置，系统和方法。 在一个示例中，控制器包括用于接收包括有效载荷数据，命名空间标识符（ID）和第一扩展逻辑块地址（LBA））的写操作的逻辑，使用有效载荷CRC计算第一系统循环冗余校验（CRC）， 命名空间ID和第一扩展LBA，在本地存储器中存储与第一扩展LBA相关联的第一系统CRC，并将有效载荷数据，第一系统CRC和从第一扩展LBA导出的截断的LBA写入存储器。 还公开并要求保护其他实例。
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