公开(公告)号：US11239199B2

公开(公告)日：2022-02-01

申请号：US15774906

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US11955462B2

公开(公告)日：2024-04-09

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.