公开(公告)号：US11239199B2

公开(公告)日：2022-02-01

申请号：US15774906

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US11469213B2

公开(公告)日：2022-10-11

申请号：US16325970

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Klaus Reingruber ,  Bernd Waidhas ,  Andreas Wolter

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L29/06 ,  H01L23/31

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US11424209B2

公开(公告)日：2022-08-23

申请号：US16871325

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20180150156A1

公开(公告)日：2018-05-31

申请号：US15879729

申请日：2018-01-25

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Teodora Ossiander ,  Andreas Wolter ,  Sonja Koller ,  Georg Seidemann ,  Jan Proschwitz ,  Hans-Joachim Barth ,  Bastiaan Elshof

IPC: G06F3/044 ,  G06F3/045 ,  G06F3/042 ,  G01L1/24 ,  G06F3/0354 ,  G06F3/038 ,  H04B1/3827 ,  G06F1/16

CPC classification number: G06F3/044 ,  G01L1/24 ,  G06F1/163 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F2203/04102 ,  G06F2203/04109 ,  H04B1/385

Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.

公开(公告)号：US09653439B2

公开(公告)日：2017-05-16

申请号：US14778036

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Sven Albers ,  Andreas Wolter ,  Klaus Reingruber ,  Thorsten Meyer

IPC: H01L25/16 ,  H01L21/50 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L23/31 ,  H01L21/683 ,  H01L23/498 ,  H01L49/02

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

公开(公告)号：US09921694B2

公开(公告)日：2018-03-20

申请号：US14778142

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Teodora Ossiander ,  Andreas Wolter ,  Sonja Koller ,  Georg Seidemann ,  Jan Proschwitz ,  Hans-Joachim Barth ,  Bastiaan Elshof

IPC: G09G5/00 ,  G06F3/044 ,  H04B1/3827 ,  G01L1/24 ,  G06F1/16 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F3/0354

CPC classification number: G06F3/044 ,  G01L1/24 ,  G06F1/163 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F2203/04102 ,  G06F2203/04109 ,  H04B1/385

Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.

公开(公告)号：US20160240435A1

公开(公告)日：2016-08-18

申请号：US14623687

申请日：2015-02-17

Applicant: Intel Corporation

Inventor： Christian Geissler ,  Klaus Reingruber ,  Sven Albers

IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49816 ,  H01L2924/15159 ,  H01L2924/15311

Abstract: An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate.

Abstract translation: 可以制造互连适配器，其具有基本上平坦的表面，微电子封装可以电连接到该表面，以及具有从互连适配器平面到互连适配器非平面表面延伸的至少一个互连的非平面表面。 互连适配器非平面表面可以被成形为基本上符合其可以附着的微电子衬底的形状，这消除了使微电子封装弯曲或以其它方式适应于符合微电子衬底的需要。

公开(公告)号：US11955462B2

公开(公告)日：2024-04-09

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20170278778A1

公开(公告)日：2017-09-28

申请号：US15622552

申请日：2017-06-14

Applicant: INTEL CORPORATION

Inventor： Christian Geissler ,  Klaus Reingruber ,  Sven Albers

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49816 ,  H01L2924/15159 ,  H01L2924/15311

Abstract: An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate.

公开(公告)号：US09711492B2

公开(公告)日：2017-07-18

申请号：US14778036

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Sven Albers ,  Andreas Wolter ,  Klaus Reingruber ,  Thorsten Meyer

IPC: H01L25/16 ,  H01L21/50 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L23/31 ,  H01L21/683 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/50 ,  H01L28/00 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.