公开(公告)号：US20230103023A1

公开(公告)日：2023-03-30

申请号：US17448716

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Martin OSTERMAYR ,  Joachim SINGER ,  Klaus HEROLD

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor die is provided. The semiconductor die comprises a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure. A top surface of the electrically conductive structure is contacted at the front side of the semiconductor substrate and a bottom surface of the electrically conductive structure is contacted at a backside of the semiconductor substrate. Further, the semiconductor die comprises a backside metallization layer stack attached to the backside of the semiconductor substrate. A first portion of a wiring structure is formed in a first metallization layer of the backside metallization layer stack and a second portion of the wiring structure is formed in a second metallization layer of the backside metallization layer stack. Further, a tapered vertical connection is formed between the first portion of the wiring structure and the second portion of the wiring structure, wherein the first metallization layer is closer to the semiconductor substrate than the second metallization layer. A width of the tapered vertical connection increases towards the first metallization layer.

公开(公告)号：US20230197537A1

公开(公告)日：2023-06-22

申请号：US17644801

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Klaus HEROLD ,  Harald GOSSNER ,  Martin OSTERMAYR ,  Georgios PANAGOPOULOS ,  Johannes RAUH ,  Joachim SINGER ,  Thomas WAGNER

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/32 ,  H01L23/481

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

公开(公告)号：US20230197566A1

公开(公告)日：2023-06-22

申请号：US17644802

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Wolfgang MOLZER ,  Peter BAUMGARTNER ,  Thomas WAGNER ,  Joachim SINGER ,  Klaus HEROLD ,  Michael LANGENBUCH

IPC: H01L23/433 ,  H01L23/473 ,  H01L23/40 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L21/4871 ,  H01L23/473 ,  H01L23/4012 ,  H01L2023/4068

Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.

公开(公告)号：US20230094594A1

公开(公告)日：2023-03-30

申请号：US17448732

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Wolfgang MOLZER ,  Klaus HEROLD ,  Joachim SINGER ,  Peter BAUMGARTNER ,  Michael LANGENBUCH ,  Thomas WAGNER ,  Bernd WAIDHAS

IPC: H01L25/065 ,  H01L27/088 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.