公开(公告)号：US20190036531A1

公开(公告)日：2019-01-31

申请号：US16146326

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Alexey KOSTINSKY ,  Nadav BONEN

IPC: H03K19/0175 ,  G06F13/16 ,  G06F3/06

CPC classification number: H03K19/017545 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1668 ,  Y02D10/14

Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

公开(公告)号：US20170077928A1

公开(公告)日：2017-03-16

申请号：US15359573

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Nadav BONEN ,  Christopher E. COX ,  Alexey KOSTINSKY

IPC: H03K19/00 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

Abstract translation: 存储器子系统包括多器件封装，其包括被组织为多级存储器的多个存储器件。 用于存储器子系统的控制单元向存储器的一些或全部行同时发送存储器访问命令，并且触发接收存储器访问命令的所有存储器等级的一部分以改变管芯终端（ODT）设置。 选择其中一个行执行存储器访问命令，并且在所有等级触发以改变ODT设置的情况下执行命令具有改变的ODT设置。

公开(公告)号：US20180025773A1

公开(公告)日：2018-01-25

申请号：US15639725

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  John B. HALBERT ,  Nadav BONEN ,  Tomer LEVY

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4087

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

公开(公告)号：US20170300415A1

公开(公告)日：2017-10-19

申请号：US15442470

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Nadav BONEN ,  Zvika GREENFIELD ,  Randy Osborne

IPC: G06F12/08 ,  G06F13/16

Abstract: Described herein are embodiments of asymmetric memory management to enable high bandwidth accesses. In embodiments, a high bandwidth cache or high bandwidth region can be synthesized using the bandwidth capabilities of more than one memory source. In one embodiment, memory management circuitry includes input/output (I/O) circuitry coupled with a first memory and a second memory. The I/O circuitry is to receive memory access requests. The memory management circuitry also includes logic to determine if the memory access requests are for data in a first region of system memory or a second region of system memory, and in response to a determination that one of the memory access requests is to the first region and a second of the memory access requests is to the second region, access data in the first region from the cache of the first memory and concurrently access data in the second region from the second memory.

公开(公告)号：US20170194962A1

公开(公告)日：2017-07-06

申请号：US15462664

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Nadav BONEN ,  Christopher E. COX ,  Alexey KOSTINSKY

IPC: H03K19/00 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.