公开(公告)号：US20250113434A1

公开(公告)日：2025-04-03

申请号：US18374617

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Bai NIE ,  Mitchell PAGE ,  Junxin WANG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Haifa HARIRI ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Hongxia FENG ,  Haobo CHEN ,  Bohan SHAN ,  Hiroki TANAKA ,  Leonel R. ARANA ,  Yonggang Yong LI

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.

公开(公告)号：US20240243066A1

公开(公告)日：2024-07-18

申请号：US18622511

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20240105571A1

公开(公告)日：2024-03-28

申请号：US17954288

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Haobo CHEN ,  Bai NIE ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/15

Abstract: Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20240332125A1

公开(公告)日：2024-10-03

申请号：US18128848

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Clay ARRINGTON ,  Bohan SHAN ,  Haobo CHEN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying XU ,  Bai NIE

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/3737 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/24 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20210028101A1

公开(公告)日：2021-01-28

申请号：US16522483

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Bai NIE ,  Haobo CHEN ,  Gang DUAN ,  Brandon C. MARIN ,  Srinivas PIETAMBARAM

IPC: H01L23/498 ,  H01L23/66 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of making such packages. In an embodiment, a package substrate comprises a substrate comprising a first dielectric material, a first trace embedded in the substrate, and a patch in direct contact with the first trace. In an embodiment, the patch comprises a second dielectric material that is different than the first dielectric material.

公开(公告)号：US20240184209A1

公开(公告)日：2024-06-06

申请号：US18060593

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Bai NIE ,  Robert MAY

IPC: G03F7/20 ,  G03F7/00

CPC classification number: G03F7/201 ,  G03F7/0007 ,  G03F7/2006 ,  G03F7/2014

Abstract: The present disclosure is directed to a lithographic patterning system including a stage for supporting a substrate with a photo-definable polymer layer, a first actinic radiation source, which is configured to propagate light along a first optical axis, a first mask for patterning the propagated light from the first actinic radiation source, a second actinic radiation source, which is configured to propagate light along a second optical axis, and a second mask for patterning the propagated light from the second actinic radiation source. In a method, first and second propagated lights form an intersection in the photo-definable polymer layer, and a patterned semiconductor component is formed at the intersection.

公开(公告)号：US20240178145A1

公开(公告)日：2024-05-30

申请号：US18434347

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.