公开(公告)号：US20170098709A1

公开(公告)日：2017-04-06

申请号：US15127850

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： NEVILLE L. DIAS ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  ROMAN W. OLAC-VAW ,  HSU-YU CHANG ,  TING CHANG ,  RAHUL RAMASWAMY ,  PEI-CHI LIU

IPC: H01L29/78 ,  H01L29/10 ,  H03D7/14 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H03D7/1425 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/165

Abstract: An embodiment includes an apparatus comprising: a non-planar fm having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one fmFET. Other embodiments are described herein.

公开(公告)号：US20160225671A1

公开(公告)日：2016-08-04

申请号：US14914179

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： ROMAN W. OLAC-VAW ,  WALID M. HAFEZ ,  CHIA-HONG JAN ,  PEI-CHI LIU

IPC: H01L21/8234 ,  H01L23/528 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L23/5283 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/66545

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract translation: 描述了在公共基板上具有不同功函数的非平面I / O和逻辑半导体器件以及在公共基板上制造具有不同功函数的非平面I / O和逻辑半导体器件的方法。 例如，半导体结构包括设置在基板上方的第一半导体器件。 第一半导体器件具有导电类型，并且包括具有第一功函数的栅电极。 半导体结构还包括设置在基板上方的第二半导体器件。 第二半导体器件具有导电类型，并且包括具有第二不同功函数的栅电极。