公开(公告)号：US20210305245A1

公开(公告)日：2021-09-30

申请号：US16833094

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Richard HUDECZEK ,  Philipp RIESS ,  Richard GEIGER ,  Peter BAUMGARTNER

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.

公开(公告)号：US20250007145A1

公开(公告)日：2025-01-02

申请号：US18216315

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Richard GEIGER ,  Georgios C. DOGIAMIS ,  Steven CALLENDER ,  Telesphor KAMGAING ,  Jonathan C. JENSEN ,  Harald GOSSNER

IPC: H01Q1/22 ,  H01L25/10 ,  H01Q21/24

Abstract: Embodiments disclosed herein include communication dies for mm-wave and/or sub-terahertz wavelength communications. In an embodiment, a communications die comprises a substrate with a first face and a second face. In an embodiment, edge surfaces connect the first face to the second face. In an embodiment, a circuitry element is on the first face, and an antenna on at least one of the edge surfaces.

公开(公告)号：US20250006837A1

公开(公告)日：2025-01-02

申请号：US18214904

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Peter BAUMGARTNER

IPC: H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/423

Abstract: Structures having vertical-transport field effect transistors (FETs) with bottom source connection are described. In an example, an integrated circuit structure includes a channel structure above a substrate. A gate structure is laterally surrounding the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically beneath the channel structure. A conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.

公开(公告)号：US20250006667A1

公开(公告)日：2025-01-02

申请号：US18341916

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Georgios PANAGOPOULOS ,  Steven CALLENDER ,  Richard GEIGER ,  Georgios C. DOGIAMIS ,  Manisha DUTTA ,  Stefano PELLERANO

IPC: H01L23/66 ,  H01L29/16 ,  H01L29/20 ,  H03F3/195 ,  H03F3/213

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package for wideband sub-terahertz communication, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, that are implemented within a layer of III-V material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197537A1

公开(公告)日：2023-06-22

申请号：US17644801

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Klaus HEROLD ,  Harald GOSSNER ,  Martin OSTERMAYR ,  Georgios PANAGOPOULOS ,  Johannes RAUH ,  Joachim SINGER ,  Thomas WAGNER

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/32 ,  H01L23/481

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.