-
公开(公告)号：US20190095316A1
公开(公告)日：2019-03-28
申请号：US15714963
申请日：2017-09-25
Applicant: INTEL CORPORATION
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive debug trace information via one or more pins, generate a packet comprising the debug trace information and a header, the header comprising header information to send the packet to a device coupled via one or more network connections, determine a location in a data buffer of an interface controller for the packet, and write the packet to the data buffer of the interface controller at the location.
-
公开(公告)号：US20180098136A1
公开(公告)日：2018-04-05
申请号：US15281233
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： RAMAMURTHY KRITHIVAS , DONGLAI DAI , RUSSELL WUNDERLICH , ESWARAMOORTHI NALLUSAMY
IPC: H04Q9/00
CPC classification number: H04Q9/00 , H04Q9/04 , H04Q2209/826 , H04Q2209/845
Abstract: The present disclosure is directed to push telemetry data accumulation. A system may comprise at least telemetry circuitry configured to push telemetry data (e.g., provide telemetry data without first receiving a request). An example system may comprise one or more devices that include at least one set of telemetry circuitry. The at least one set of telemetry circuitry may be configured to push data based at least on a frequency configuration and a skew configuration. The frequency configuration may control how often the at least one set of telemetry circuitry generates data. The skew configuration may control when the telemetry data is transmitted. For example, sets of telemetry circuitry may be configured with different skew configurations to minimize transmission overlap. This may prevent telemetry data accumulation (TDA) circuitry in the system, which receives the transmission of telemetry data from the at least one set of telemetry circuitry, from becoming overwhelmed.
-
公开(公告)号：US20200004713A1
公开(公告)日：2020-01-02
申请号：US16566576
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： BALAJI PARTHASARATHY , RAMAMURTHY KRITHIVAS , BRADLEY BURRES , PAWEL SZYMANSKI , Yi-Feng LIU
IPC: G06F13/40 , G06F9/4401 , G06F9/445
Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.
-
Patent Agency Ranking
公开(公告)号：US20160179383A1
公开(公告)日：2016-06-23
申请号：US14580008
申请日：2014-12-22
Applicant: Intel Corporation
Inventor： RAMAMURTHY KRITHIVAS , ESWARAMOORTHI NALLUSAMY , MARK A. SCHMISSEUR
CPC classification number: G06F12/0692 , G06F9/45541 , G06F9/5077 , G06F2212/1041 , G06F2212/657
Abstract: Apparatus, systems, and methods to implement a virtual serial presence detect operation for pooled memory are described. In one embodiment, a controller comprises logic to receive a request to establish a composed computing device, define a plurality of virtual memory devices to be associated with a composed computing device, allocate memory from a shared pool of physical memory to the plurality of virtual memory devices, create a plurality of virtual serial detects (vSPDs) for the plurality of virtual memory devices, and store the plurality of vSPDs in a linked list in an operational memory device. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了用于实现池存储器的虚拟串行存在检测操作的装置，系统和方法。 在一个实施例中，控制器包括接收建立组合计算设备的请求的逻辑，定义要与组合计算设备相关联的多个虚拟存储器设备，将存储器从物理存储器的共享池分配给多个虚拟存储器 设备，为多个虚拟存储设备创建多个虚拟串行检测（vSPD），并将多个vSPD存储在操作存储器设备中的链表中。 还公开并要求保护其他实施例。
-
5.发明申请公开(公告)号：US20190094946A1
公开(公告)日：2019-03-28
申请号：US15719276
申请日：2017-09-28
Applicant: INTEL CORPORATION
Inventor： BHARAT S. PILLILLI , ESWARAMOORTHI NALLUSAMY , RAMAMURTHY KRITHIVAS , VIVEK GARG , VENKATESH RAMAMURTHY
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.
-
公开(公告)号：US20180285289A1
公开(公告)日：2018-10-04
申请号：US15476901
申请日：2017-03-31
Applicant: INTEL CORPORATION
Inventor： JEFFREY A. PIHLMAN , RAMAMURTHY KRITHIVAS
CPC classification number: G06F13/1668 , G06F9/4401
Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.
-
公开(公告)号：US20170161111A1
公开(公告)日：2017-06-08
申请号：US15432826
申请日：2017-02-14
Applicant: Intel Corporation
Inventor： RAMAMURTHY KRITHIVAS , BALAJI PARTHASARATHY
CPC classification number: G06F9/5011 , G06F1/26 , G06F9/4411 , G06F9/4418 , G06F9/44505 , G06F9/5072 , G06F9/5077 , G06F9/546 , G06F13/126
Abstract: The present disclosure is directed to hardware-based inter-device resource sharing. For example, a remote orchestrator (RO) may provide instructions to cause a device to make at least one hardware resource available to other devices. An RO module in the device may interact with the RO and may configure a configuration module in the device based on instructions received from the RO. The configuration module may set a device configuration when the device transitions from a power off state to a power on state. The device may also comprise a processing module to process data based on the device configuration, interface technology (IT) and at least one hardware resource. The interface technology may allow the processing module and the at least one hardware resource to interact. The RO module may configure the IT to allow the at least one hardware resource to operate locally or remotely based on the instructions.
-
公开(公告)号：US20160274941A1
公开(公告)日：2016-09-22
申请号：US14659523
申请日：2015-03-16
Applicant: Intel Corporation
Inventor： RAMAMURTHY KRITHIVAS , BALAJI PARTHASARATHY
CPC classification number: G06F9/5011 , G06F1/26 , G06F9/4411 , G06F9/4418 , G06F9/44505 , G06F9/5072 , G06F9/5077 , G06F9/546 , G06F13/126
Abstract: The present disclosure is directed to hardware-based inter-device resource sharing. For example, a remote orchestrator (RO) may provide instructions to cause a device to make at least one hardware resource available to other devices. An RO module in the device may interact with the RO and may configure a configuration module in the device based on instructions received from the RO. The configuration module may set a device configuration when the device transitions from a power off state to a power on state. The device may also comprise a processing module to process data based on the device configuration, interface technology (IT) and at least one hardware resource. The interface technology may allow the processing module and the at least one hardware resource to interact. The RO module may configure the IT to allow the at least one hardware resource to operate locally or remotely based on the instructions.
Abstract translation: 本公开涉及基于硬件的设备间资源共享。 例如，远程协调器（RO）可以提供指令以使设备使至少一个硬件资源可用于其他设备。 设备中的RO模块可以与RO交互，并且可以基于从RO接收到的指令在设备中配置配置模块。 当设备从电源关闭状态转换到电源接通状态时，配置模块可以设置设备配置。 该设备还可以包括用于基于设备配置，接口技术（IT）和至少一个硬件资源来处理数据的处理模块。 接口技术可以允许处理模块和至少一个硬件资源进行交互。 RO模块可以将IT配置为允许至少一个硬件资源基于指令在本地或远程操作。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.022 seconds)
