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    TECHNOLOGIES FOR MANAGING A DYNAMIC READ CACHE OF A SOLID STATE DRIVE
    4.
    发明申请
    TECHNOLOGIES FOR MANAGING A DYNAMIC READ CACHE OF A SOLID STATE DRIVE 审中-公开
    用于管理固态驱动器的动态读取速度的技术

    公开(公告)号：US20170075812A1

    公开(公告)日：2017-03-16

    申请号：US14855660

    申请日：2015-09-16

    Applicant: Intel Corporation

    Inventor： Ning Wu ,  Dale J. Juenemann ,  Neeraj Sharma ,  Ramkarthik Ganesan

    IPC: G06F12/08

    CPC classification number: G06F12/0893 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/222 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7207

    Abstract: Technologies for managing a read cache of a solid state drive include establishing a read cache in an otherwise unused region of non-volatile memory of the solid state drive. To do so, a memory region of the non-volatile memory corresponding to the read cache is converted to single-level cell (SLC) mode. For example, the memory region may be converted from a multi-level cell (MLC) or a triple-level cell (TLC) mode to the SLC mode. A drive controller of the solid state drive manages data in the read cache based on a read count associated with the data. For example, data having a relatively high read count may be inserted into the read cache and data having a relatively lower read count may be evicted from the read cache over time. The size of the read cache may be dynamically adjusted over time based on available space and/or operating requirements.

    Abstract translation: 用于管理固态驱动器的读取高速缓存的技术包括在固态驱动器的非易失性存储器的另外未使用的区域中建立读高速缓存。 为此，将与读取的高速缓存相对应的非易失性存储器的存储器区域转换为单级单元（SLC）模式。 例如，存储器区域可以从多级单元（MLC）或三级单元（TLC）模式转换为SLC模式。 固态驱动器的驱动器控制器基于与数据相关联的读取计数来管理读取高速缓存中的数据。 例如，具有较高读取计数的数据可被插入到读取的高速缓冲存储器中，具有较低读取计数的数据可以随着时间从读取的高速缓存中逐出。 读取缓存的大小可以根据可用空间和/或操作要求随时间动态调整。

    Data recovery in memory devices
    5.
    发明授权
    Data recovery in memory devices 有权

    公开(公告)号：US10303571B2

    公开(公告)日：2019-05-28

    申请号：US14932870

    申请日：2015-11-04

    Applicant: Intel Corporation

    Inventor： Ning Wu ,  Xin Guo ,  Ramkarthik Ganesan ,  Pranav Kalavade ,  Robert Frickey

    IPC: G06F11/00 ,  G06F11/20 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804 ,  G06F12/0868

    Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

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