公开(公告)号：US20170178708A1

公开(公告)日：2017-06-22

申请号：US15371122

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  Wei WU ,  Shih-Lien LU ,  James W. TSCHANZ ,  Georgios PANAGOPOULOS ,  Helia NAEIMI

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

公开(公告)号：US20250006667A1

公开(公告)日：2025-01-02

申请号：US18341916

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Georgios PANAGOPOULOS ,  Steven CALLENDER ,  Richard GEIGER ,  Georgios C. DOGIAMIS ,  Manisha DUTTA ,  Stefano PELLERANO

IPC: H01L23/66 ,  H01L29/16 ,  H01L29/20 ,  H03F3/195 ,  H03F3/213

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package for wideband sub-terahertz communication, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, that are implemented within a layer of III-V material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230197537A1

公开(公告)日：2023-06-22

申请号：US17644801

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard GEIGER ,  Klaus HEROLD ,  Harald GOSSNER ,  Martin OSTERMAYR ,  Georgios PANAGOPOULOS ,  Johannes RAUH ,  Joachim SINGER ,  Thomas WAGNER

IPC: H01L21/66 ,  H01L23/48

CPC classification number: H01L22/32 ,  H01L23/481

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.