公开(公告)号：US10310989B2

公开(公告)日：2019-06-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US20170357462A1

公开(公告)日：2017-12-14

申请号：US15176650

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Benjamin L. Walker ,  August A. Camber ,  Jonathan Bryan Stern ,  Sanjeev Trika ,  Richard P. Mangold ,  Jawad Basit Khan ,  Anand Ramalingam

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0683 ,  G06F12/06 ,  G06F12/0623 ,  G06F17/30185 ,  G06F2212/1056 ,  G06F2212/261 ,  G06F2212/401

Abstract: In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is further to identify a memory location after a last segment of the data log, append the data to the data log by writing the data to the memory location after the last segment of the data log, and provide, to the computing host, a key comprising an identification of the memory location at which the data was appended to the data log.

公开(公告)号：US20190258414A1

公开(公告)日：2019-08-22

申请号：US16405296

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC: G06F3/06 ,  G06F12/02

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.

公开(公告)号：US10073659B2

公开(公告)日：2018-09-11

申请号：US14751846

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： James Alexander ,  Muthukumar P. Swaminathan ,  Richard P. Mangold

IPC: G06F1/26 ,  G06F1/32 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0673 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/329 ,  G06F3/0625 ,  G06F3/0653 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/24

Abstract: A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.

公开(公告)号：US20150154124A1

公开(公告)日：2015-06-04

申请号：US14093772

申请日：2013-12-02

Applicant: Intel Corporation

Inventor： Shamanna Datta ,  Mark A. Schmisseur ,  Murugasamy Nachimuthu ,  Richard P. Mangold ,  Mahesh S. Natu

IPC: G06F12/14 ,  G06F11/10

CPC classification number: G06F12/0246 ,  G06F12/084 ,  G06F2212/7202

Abstract: Apparatus, systems, and methods to implement a secure data partition in memory systems are described. In one example, a controller comprises logic to receive, in a system management mode mailbox, a memory partition creation request from a system management mode interface, wherein the memory partition creation request comprises at least one characteristic of a memory partition, authenticate the partition creation request and create a memory partition in a memory coupled to the controller in accordance with the at least one characteristic. Other examples are also disclosed and claimed.

Abstract translation: 描述了在存储器系统中实现安全数据分区的装置，系统和方法。 在一个示例中，控制器包括在系统管理模式邮箱中从系统管理模式接口接收存储器分区创建请求的逻辑，其中所述存储器分区创建请求包括存储器分区的至少一个特征，认证分区创建 请求并根据该至少一个特性在耦合到控制器的存储器中创建存储器分区。 还公开并要求保护其他实例。

公开(公告)号：US20140223231A1

公开(公告)日：2014-08-07

申请号：US13976002

申请日：2012-06-07

Applicant: INTEL CORPORATION

Inventor： Richard P. Mangold ,  Richard L. Coulson ,  Robert J. Royer, JR. ,  Sanjeev N. Trika

IPC: G06F11/07 ,  G11C16/16 ,  G06F3/06

CPC classification number: G11C16/16

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在功率损耗恢复中用于固态驱动器管理的设备，方法，计算机可读介质和系统配置。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10067879B2

公开(公告)日：2018-09-04

申请号：US14972053

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Woojong Han ,  Andy M. Rudoff ,  Mark A. Schmisseur ,  Richard P. Mangold

IPC: G06F12/08 ,  G06F12/1009 ,  G06F12/0877 ,  G06F12/0893

Abstract: Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

公开(公告)号：US09817738B2

公开(公告)日：2017-11-14

申请号：US14845503

申请日：2015-09-04

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Camille C. Raad ,  Richard P. Mangold ,  Theodros Yigzaw

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G11C29/42 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1612 ,  G06F11/167 ,  G06F12/00 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

Abstract: Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.

公开(公告)号：US20170168747A1

公开(公告)日：2017-06-15

申请号：US14966933

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Woojong Han ,  John V. Lovelace ,  Priscilla Y. Lam ,  Richard P. Mangold ,  Asher M. Altman ,  Shachi K. Thakkar

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F9/4405 ,  G06F1/24

Abstract: Embodiments are generally directed to intelligent memory support for platform reset operation. An embodiment of a memory module includes a memory module controller and one or more memory banks. The memory module controller is to perform one or more internal reset processes as required for the memory module, and is to support a plurality of host platform reset processes to synchronize with the host platform.

公开(公告)号：US10915254B2

公开(公告)日：2021-02-09

申请号：US16405296

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Kunal A. Khochare ,  Camille C. Raad ,  Richard P. Mangold ,  Shachi K. Thakkar

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0866 ,  G06F11/16 ,  G06F11/00 ,  G06F12/0888

Abstract: Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.