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公开(公告)号：US09396065B2
公开(公告)日：2016-07-19
申请号：US14314181
申请日：2014-06-25
Applicant: Intel Corporation
Inventor： Randall K. Webb , Jawad B. Khan , Richard L. Coulson , Knut S. Grimsrud , Brian M. Yablon
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0688 , G06F11/1008 , G06F11/1016 , G06F11/1068 , G06F12/0246 , G06F2212/7201
Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.
Abstract translation: 本公开涉及可扩展存储器集线器。 装置可以包括第一可扩展非易失性存储器（NVM）集线器（EN集线器）。 第一个EN集线器包括被配置为将第一EN集线器耦合到NVM控制器或第二EN集线器的上游接口端口; 下游接口端口，被配置为将第一EN集线器耦合到第三EN集线器或NVM设备; 至少一个NVM设备端口，每个NVM设备端口被配置为经由NVM信道将所述第一EN集线器耦合到相应的NVM设备; 和一个EN集线器控制器。 EN集线器控制器包括命令逻辑，其被配置为响应于来自NVM控制器的初始化链命令来初始化第一EN集线器，初始化包括枚举耦合到第一EN集线器的每个NVM设备以及一个或多个相关联的NVM管芯中的每一个。
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公开(公告)号：US11500887B2
公开(公告)日：2022-11-15
申请号：US17227045
申请日：2021-04-09
Applicant: Intel Corporation
Inventor： Sourabh Dongaonkar , Jawad B. Khan , Chetan Chauhan , Dipanjan Sengupta , Mariano Tepper , Theodore Willke , Richard L. Coulson
IPC: G06F16/24 , G06F16/2458 , G06N7/00 , G06F16/21 , G06F16/22 , G06F16/248
Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.
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公开(公告)号：US20170322746A1
公开(公告)日：2017-11-09
申请号：US15462278
申请日：2017-03-17
Applicant: Intel Corporation
Inventor： Jawad B. Khan , Knut S. Grimsrud , Richard L. Coulson
CPC classification number: G06F3/0641 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/0659 , G06F3/0688 , G06F17/30109 , G06F2003/0697 , G06F2212/402
Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.
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4.发明申请STORAGE CACHE PERFORMANCE BY USING COMPRESSIBILITY OF THE DATA AS A CRITERIA FOR CACHE INSERTION 审中-公开通过使用数据的可靠性作为缓存执行标准的存储缓存性能公开(公告)号：US20160283390A1
公开(公告)日：2016-09-29
申请号：US14672093
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Richard L. Coulson
IPC: G06F12/08
CPC classification number: G06F12/0868 , G06F12/0871 , G06F12/123 , G06F12/127 , G06F2212/1021 , G06F2212/222 , G06F2212/401
Abstract: Methods and apparatus related to improving storage cache performance by using compressibility of the data as a criteria for cache insertion or allocation and deletion are described. In one embodiment, memory stores one or more cache lines corresponding to a compressed version of data (e.g., in response to a determination that the data is compressible). It is determined whether the one or more cache lines are to be retained or inserted in the memory based at least in part on an indication of compressibility of the data. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了通过使用数据的可压缩性作为缓存插入或分配和删除的标准来改善存储高速缓存性能的方法和装置。 在一个实施例中，存储器存储对应于数据的压缩版本的一个或多个高速缓存行（例如，响应于确定数据是可压缩的）。 至少部分地基于数据的可压缩性的指示确定一个或多个高速缓存行是要被保留还是插入到存储器中。 还公开并要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20140223231A1
公开(公告)日：2014-08-07
申请号：US13976002
申请日：2012-06-07
Applicant: INTEL CORPORATION
Inventor： Richard P. Mangold , Richard L. Coulson , Robert J. Royer, JR. , Sanjeev N. Trika
CPC classification number: G11C16/16
Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了在功率损耗恢复中用于固态驱动器管理的设备，方法，计算机可读介质和系统配置。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US10120608B2
公开(公告)日：2018-11-06
申请号：US15462278
申请日：2017-03-17
Applicant: Intel Corporation
Inventor： Jawad B. Khan , Knut S. Grimsrud , Richard L. Coulson
Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.
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公开(公告)号：US09619167B2
公开(公告)日：2017-04-11
申请号：US14091598
申请日：2013-11-27
Applicant: Intel Corporation
Inventor： Jawad B. Khan , Knut S. Grimsrud , Richard L. Coulson
CPC classification number: G06F3/0641 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/0659 , G06F3/0688 , G06F17/30109 , G06F2003/0697 , G06F2212/402
Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.
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8.发明授权公开(公告)号：US11657889B2
公开(公告)日：2023-05-23
申请号：US16827235
申请日：2020-03-23
Applicant: Intel Corporation
Inventor： Jawad B. Khan , Richard L. Coulson , Zion S. Kwok , Ravi H. Motwani
CPC classification number: G11C29/42 , G11C5/025 , G11C11/409 , G11C29/021 , G11C29/44 , G11C2029/1204
Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.
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公开(公告)号：US10372339B2
公开(公告)日：2019-08-06
申请号：US15175697
申请日：2016-06-07
Applicant: Intel Corporation
Inventor： Randall K. Webb , Jawad B. Khan , Richard L. Coulson , Knut S. Grimsrud , Brian M. Yablon
Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.
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