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    Constant Buffer Size Multi-Sampled Anti-Aliasing Depth Compression
    2.
    发明申请
    Constant Buffer Size Multi-Sampled Anti-Aliasing Depth Compression 有权
    恒定缓冲区大小多采样抗锯齿深度压缩

    公开(公告)号：US20160086374A1

    公开(公告)日：2016-03-24

    申请号：US14492173

    申请日：2014-09-22

    Applicant: Intel Corporation

    Inventor： Robert L. Farrell ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Karol A. Szerszen

    IPC: G06T15/40 ,  G06T9/00 ,  G06T5/00

    CPC classification number: G06T15/405 ,  G06T5/002 ,  G06T9/00 ,  G06T11/40

    Abstract: By packing the depth data in a way that is independent of the number of samples, so that memory bandwidth is the same regardless of the number of samples, higher numbers of samples per pixel may be used without adversely affecting buffer cost. In some embodiments, the number of pixels per clock in a first level depth test may be increased by operating in the pixel domain, whereas previous solutions operated at the sample level.

    Abstract translation: 通过以独立于样本数量的方式打包深度数据，使得存储器带宽相同，而不考虑样本数量，可以使用每像素更多的采样数，而不会不利地影响缓冲器成本。 在一些实施例中，可以通过在像素域中操作来增加第一级深度测试中每个时钟的像素数量，而先前的解决方案在采样级别下运行。

    Optimized depth buffer cache apparatus and method
    9.
    发明授权
    Optimized depth buffer cache apparatus and method 有权

    公开(公告)号：US10002455B2

    公开(公告)日：2018-06-19

    申请号：US14691517

    申请日：2015-04-20

    Applicant: Intel Corporation

    Inventor： Robert L. Farrell ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Karol A. Szerszen

    IPC: G06T15/40 ,  G06T15/00

    CPC classification number: G06T15/005

    Abstract: An apparatus and method are described for performing efficient depth test operations. For example, an apparatus in accordance with one embodiment comprises: a depth cache to store a plurality of cache lines containing depth data to be used for graphics processing operations; depth test logic to determine a current depth test function associated with a read operation and to read a cache line from a depth cache while there are still outstanding writes to the cache line if the read operation and write operation are associated with the same depth test function, the depth test logic to perform a first depth test using the data read from the cache line, the first depth test to fail or pass pixels based on a predicted range of depth values.

    Four corner high performance depth test
    10.
    发明授权
    Four corner high performance depth test 有权
    四角高性能深度测试

    公开(公告)号：US09569882B2

    公开(公告)日：2017-02-14

    申请号：US14136290

    申请日：2013-12-20

    Applicant: Intel Corporation

    Inventor： Robert L. Farrell ,  Vasanth Ranganathan ,  Karol A. Szerszen

    IPC: G06T15/40

    CPC classification number: G06T15/405 ,  G06T2210/12

    Abstract: One or more apparatus and method for multi-pixel/sample level depth testing in a graphics processor is described. In embodiments, a bounding-box of variable size over which a depth test is to be performed is determined based on the pattern of lit pixels or samples within rasterizer tile. A multi-corner depth test may be performed between a source depth data plane and a destination depth plane within a source depth data bound where destination depth data is continuous within the source data bound. A range-based depth test may be performed in response to the destination data being discontinuous. Source depth data prevailing in the depth test may be stored in a compressed plane equation format in response to the source data being continuous within the source data bound, and may be stored as min/max depth data if discontinuous.

    Abstract translation: 描述了一种或多种用于图形处理器中的多像素/样本级深度测试的装置和方法。 在实施例中，基于在光栅化器瓦片内的点亮像素或样本的图案来确定将要执行深度测试的可变大小的边界框。 可以在源深度数据边界内的源深度数据平面和目的地深度平面之间执行多角度深度测试，其中目的地深度数据在源数据界限内是连续的。 可以响应于不连续的目的地数据来执行基于范围的深度测试。 在深度测试中存在的源深度数据可以以压缩平面方程式格式存储，以响应于源数据界限内的源数据是连续的，并且如果不连续，则可以将其存储为最小/最大深度数据。

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